u/which-char

I have access to a commercial process node. The NDA broadly restricts "publishing details about the technology" but doesn't spell out exactly what that covers.

I'm trying to publish a paper comparing two RTL implementations run through the same PDK. I want to report things like post-route power (mW) and relative timing margin between the two designs, without naming the specific node, foundry, or reporting absolute standard-cell area / instance counts.

For anyone who's navigated something similar:

- Have you published or presented post-layout/post-route power or timing numbers derived from an NDA'd PDK, even without naming the node?

PS: Lust curious what's actually common practice in academic/research publishing. Appreciate your response.

Thanks!

Hi everyone,

I’m an Indian citizen currently studying at a university in Germany. I am planning to publish a paper at IEEE.

Their registration fees are divided into two categories:

• SAARC (including India) — fee in INR
• Other Countries — fee in USD

Also my research paper is not affiliated with a German university.

Has anyone been in a similar situation with an IEEE conference in India?

Would I normally qualify for the SAARC/Indian registration fee based on my Indian citizenship, or would I be considered an international author because my university affiliation is in Germany?

Thanks!

Hi,
I am currently learning custom layout in Cadence Virtuoso using the GF22FDX / 22FDX SOI PDK and running Calibre DRC. I am trying to layout a simple CMOS inverter, but I am stuck on a DRC error related to the PC-to-M1 contact at the input/gate connection.

This looks like the CB/contact cut inside the PCCBM1 via. The contact is placed at the Vin gate connection where Metal1 connects to PC/poly.

I tried increasing the PC width and changing the path end style to variable with extra extension. The PC path now seems to enclose the contact better, but the same DRC error still appears after rerunning DRC.

My questions are:

1. Is this error saying that the CB contact cut is not sufficiently enclosed by PC/poly?
2. Should I fix this by manually increasing the PC landing area, or should I delete and recreate the PCCBM1 via using the PDK via generator?
3. In GF22FDX, are there special restrictions for PC/poly contacts where simply drawing a larger PC rectangle around the via is not enough?
4. Could this be caused by the via’s own generated enclosure parameters rather than the surrounding PC path?
5. What is the recommended way to create a legal PC-to-M1 gate contact for a simple inverter in this PDK?

I am still new to advanced-node layout rules, so I may be misunderstanding how the Calibre marker should be interpreted. Any guidance on how to debug this kind of CB/PC enclosure DRC in Virtuoso/Calibre RVE would be very helpful.

https://preview.redd.it/k0s29os1u13h1.png?width=681&format=png&auto=webp&s=e542f23eb157d8f43c35470e112eb7a94937ba74

https://preview.redd.it/kz1g2kvrr13h1.png?width=911&format=png&auto=webp&s=830f851c3eb4855f82944fa773c57765d64ced62

Thanks!!