I want to make sure the design is up to spec. This is the LDO circuit for a keyboard PCB. I plan to use the unified daughterboard, which has most ESD, resettable fuse and CC pull-ups already on it. The D+ pull-up is internal in the RP2350. For ESD safety when connecting, there is a second line of protection on this PCB. I am limiting the use of capacitors before the LDO to a maximum of 10 µF, and the LDO features a soft start for everything after that. Since the board is intended for DIY, I am adding a reverse current protection diode in case someone adds something with capacitance. Have I forgotten anything, and is the MBR130 a good choice here? I want the user to be able to add to the SK6812 leds if he wants. How can I ensure that the capacitance of any additional LED strips is still below 10 µF when there is already almost nothing left?
I have five identical SPI ADCs that sample on CS edge and then return a databit on each clock tick, so there is no MOSI. Only CLK, MISO and CS.
Are there any disadvantages to multiple MISO lines instead of multiple CS lines?
I can only see big advantages, since I can read the entire port at once anyway:
Am I missing something?
I'm designing a keyboard PCB that uses a cable-connected daughterboard with plated mounting holes. One of these mounting holes of the daugtherboard is connected to USB Shield. What is the recommended way to mount the main PCB? For robustness, I definitely want them to be plated as well. Should I leave them floating? Since this is a HE keyboard with a lot of signalling, I would prefer not to interfere with my signal ground.
However, for ESD reasons, this might result in a poor ground connection and arcs from my case to the main PCB, or poorer EMC performance. What is the standard?
I hope this question still fits with the theme of this subreddit, which is at a component level. This is an image from a lecture showing an LC filter realised with λ/8 lines with open stubs or shorts in series.
The lecturer said that this is not feasible because the green part is physically impossible. When I asked why, he replied that the return line cannot be Gnd and the path to Z4 at the same time, but I don't really understand what he meant by that. To me, this just looks like a closed stub where the return path is not Gnd, but a line connected to Z4. It may be impractical for a PCB design, but it's not impossible. Can someone explain this to me? Thank you very much!
