I’ve been building a different approach to FPGA development. Would appreciate some technical criticism
I’ve spent the last few months building Forge, a higher-level FPGA development platform, and I’ve just released the first Forge Studio pre-release for Windows and Linux.
The basic idea is that visual design, Rust and Python all feed into the same underlying hardware model and compiler architecture. Studio isn’t intended to be a separate schematic toy sitting beside the “real” workflow.
The current 0.1.0 pre-release focuses on design, validation and simulation. It includes component-based visual design, clocks and CDC, state machines, memories, streaming components, live signal values and waveform viewing.
Hardware Build is deliberately disabled in the public pre-release at the moment because the production target/backend packages aren’t ready to ship yet.
I’m mainly posting here because I’d like criticism from people who actually work with FPGAs.
Things I’m particularly interested in:
- Where would this approach fall apart on a real design?
- What would stop you using a higher-level visual/Rust/Python workflow?
- What FPGA families or boards would actually matter to you?
- What would Studio need before you’d trust it on a real project?
- Are there workflows I’m fundamentally overlooking?
Community is free if anyone wants to play with it:
I’m happy to answer questions about how the architecture works too.
