r/AIProgrammingHardware

I Tested Gemma-4 vs. the Qwen Coders on 16GB - The Bottleneck Was Never the Model (by Anubhav) is a practical, real-world comparison that challenges pure benchmark chasing. On paper, Qwen’s coder model (specifically Qwen3.6-Coder-35B-A3B) beats Gemma-4 by a solid 21 points on coding benchmarks. But when the author actually ran both on an RTX 4070 Ti Super with only 16GB VRAM against a real codebase (implementing cursor logic for an /events endpoint), that gap almost disappeared. The models became limited by the same hardware realities: painfully slow token generation from the very first output, and context windows that are “mostly fiction” - the model effectively goes blind partway through larger repos. The article’s core takeaway is that on constrained consumer hardware like 16GB VRAM, the real bottlenecks are memory management, context handling, and inference speed, not which model has the higher synthetic benchmark score. It’s a grounded reminder that for practical coding/agent use, hardware constraints often matter more than raw model quality differences.

I just got a brand new laptop and it has a NPU. I want to start experimenting with what it can do, but not necessarily using the straightforward idea of copying gpt or something like that.

I have seen in the past where the gpu had been used for something other than rendering, so my thought goes to wondering what all I can use the npu for beyond the expected.

I have several ideas in mind that I want to try, from having several agents process whether they see other, give agents small neural nets like around 12 or less nodes for specific uses such a threat evaluation in a game with hundreds of units, apply new methods to figuring out the shortest path between two nodes on a graph or the shortest route to connect all nodes in a graph, etc.

The concept of a unit that applies one operation to lots of data seems useful in all these ways, and not exclusively to LLMs. Even if the NPU is not optimized for it, if it can handle it at all, it allows for faster processing by spreading the workload on a computer.

However, I haven't found any documentation for trying to use an NPU in my own applications.

Does anyone know of a place where I can find documentation or a guide for programing c++ to use an npu?

In the fast-evolving landscape of artificial intelligence hardware, NVIDIA has established a tradition of naming its GPU architectures after pioneering scientists. Following the Blackwell era and the upcoming Rubin generation, the company unveiled its next major leap: the Feynman microarchitecture, slated for 2028. Named after the legendary physicist Richard Feynman-famous for his work in quantum mechanics and his famous lecture “There’s plenty of room at the bottom,” which foreshadowed nanotechnology-the architecture represents NVIDIA’s vision for the next phase of AI factories capable of handling gigawatt-scale systems and increasingly sophisticated agentic AI workloads.

Announced by CEO Jensen Huang at GTC 2025 and elaborated with deeper technical previews at GTC 2026, Feynman builds on the momentum of previous generations while introducing transformative changes in manufacturing, packaging, interconnects, and system-level integration. As of mid-2026, much remains under wraps-no full public specifications, exact performance figures, or pricing have been released-but authoritative reports from NVIDIA’s own announcements, detailed coverage by sites like Wccftech, Jon Peddie Research, Tom’s Hardware, and analysis from SemiAnalysis paint a clear picture of a platform designed for unprecedented scale, efficiency, and a stronger emphasis on inference alongside training.

This article synthesizes everything publicly known from reliable sources as of June 2026, focusing on the architecture’s context, technical innovations, platform ecosystem, comparisons to predecessors, and broader implications. While exact transistor counts, FLOPS ratings, or power envelopes are not yet confirmed, the direction is unmistakable: Feynman aims to push beyond the physical limits of traditional copper interconnects and planar chip designs through 3D stacking, custom high-bandwidth memory, silicon photonics, and tight integration with specialized inference accelerators.

The Road to Feynman: NVIDIA’s Accelerating Cadence

NVIDIA’s GPU roadmap has followed a roughly annual rhythm in recent years, driven by the explosive demand for AI compute. The Blackwell architecture (2024-2025) brought massive gains in AI performance with its GB200 and related SKUs on TSMC’s 4nm-class process, paired with the Grace CPU in the Grace-Blackwell Superchip. Rubin (expected 2026) and Rubin Ultra (around 2027) continue this trajectory on more advanced nodes (likely 3nm-class), introducing the Vera CPU and further optimizations for training and inference efficiency.

Feynman was first publicly positioned at GTC 2025 as the successor following Rubin. At GTC 2026, NVIDIA provided the first substantial technical preview, confirming key features and integrating it into a broader “Rosa Feynman” platform vision. NVIDIA appears to be following a yearly platform/product update rhythm, while major GPU architectures remain closer to a multi-year cadence.

This naming convention-Hopper (Grace Hopper), Blackwell (David Blackwell), Rubin (Vera Rubin), and now Feynman-honors scientists who expanded human understanding of computation, physics, and data. Richard Feynman’s contributions to quantum electrodynamics and his visionary ideas about atomic-scale engineering align perfectly with NVIDIA’s push into advanced packaging and optical technologies.

NVIDIA’s GPU Roadmap Overview (simplified, based on public announcements):

• Blackwell (2024/2025): 4nm-class, HBM3e, Grace CPU.
• Rubin (2026): Advanced 3nm-class node, HBM4, Vera CPU.
• Rubin Ultra (2027): Further refinements, higher density.
• Feynman (2028): TSMC A16 (1.6nm), 3D stacking, custom HBM, Rosa CPU + LP40 LPU.

Manufacturing Process and Design Acceleration

Several supply-chain reports have linked Feynman to TSMC’s A16-class process, but NVIDIA has not publicly confirmed the manufacturing node. This represents a significant shrink from Rubin’s likely 3nm-class process, enabling higher transistor density, better power efficiency, and performance headroom.

NVIDIA is reportedly using its own current-generation Blackwell GPUs to accelerate the design and verification of Feynman silicon-a smart bootstrapping approach that leverages existing AI infrastructure for faster iteration on future chips.

Packaging innovations are central. Feynman introduces 3D die stacking (via hybrid bonding or SoIC technology) for GPU dies-the first time NVIDIA has stacked GPU logic dies vertically in its silicon. This allows for greater compute density within a single package compared to traditional 2.5D approaches like CoWoS. Some reports suggest Intel could be involved in advanced packaging, potentially including EMIB-style interconnects, but this has not been confirmed by NVIDIA.

These choices address the fundamental challenge of scaling AI systems: more transistors and bandwidth in less space while managing power and thermals.

Core Technical Innovations

Several headline features define Feynman:

3D Die Stacking
By stacking GPU dies vertically, NVIDIA can integrate more compute resources closer together. This improves inter-die bandwidth, reduces latency, and enhances overall efficiency compared to side-by-side chiplet designs. It is a logical evolution from 2.5D packaging and a direct response to the limits of planar scaling.

Custom High-Bandwidth Memory (HBM)
Feynman moves beyond standard next-gen HBM to a custom HBM solution, potentially a proprietary variant of HBM4E or an early HBM5-class memory. Reports suggest capacities exceeding 1 TB of HBM per GPU package in some configurations, paired with significantly higher bandwidth. Some analyses mention possible integration with on-package SRAM for even faster local access.

This custom memory approach allows NVIDIA to optimize specifically for AI workloads-balancing capacity for large models with the extreme bandwidth needed for training and inference.

Optical Interconnects and Silicon Photonics
One of the most transformative shifts is the move toward co-packaged optics (CPO) and optical NVLink. Copper interconnects face physical limits in speed, distance, power consumption, and signal integrity at the scales required for future AI factories. Feynman platforms transition scale-up (within racks or clusters) toward native optical connections via NVLink switches with CPO.

This enables larger, more efficient “system-of-systems” architectures. Optical signals travel at light speed with lower power and heat, supporting the gigawatt-scale AI factories NVIDIA envisions. Spectrum-class switches with CPO handle scale-out networking.

Integration of Specialized Inference Hardware (LP40 LPU) NVIDIA has integrated Groq-derived LPU technology into its roadmap, including Groq 3 LPUs for Rubin-era systems and LP40 for the Feynman generation. Some reports describe this as an IP acquisition or licensing arrangement. LPUs are purpose-built for the decode phase of autoregressive inference, emphasizing deterministic execution, massive on-chip SRAM (hundreds of MB per chip with extremely high bandwidth like 150 TB/s in related designs), and predictable low latency-complementing GPUs’ strengths in parallel training and general compute.

The LP40 supports formats like NVFP4 and connects via NVLink for coherency with the CPU and GPU. This hybrid approach addresses the growing importance of inference in production AI systems, especially for agentic workflows requiring fast, reliable responses.

The Rosa Feynman Platform Ecosystem

Feynman does not stand alone; it is part of a full-stack platform called Rosa Feynman:

• Rosa CPU: A brand-new in-house data center CPU architecture, successor to Vera (and ultimately Grace). Named after Rosalind Franklin (the chemist and X-ray crystallographer whose work helped reveal DNA’s structure), it focuses on exceptional single-thread performance and efficient movement of data, tools, and tokens across complex agentic AI systems. NVIDIA has reportedly shortened its CPU development cycle significantly.

• Supporting Components: BlueField-5 DPU for networking/storage offload, CX10 SuperNIC, and advanced NVLink/Spectrum switches with CPO capabilities.

• Rack and System Scaling: The Kyber rack architecture (introduced or previewed earlier) scales dramatically. Coverage based on NVIDIA’s roadmap suggests Kyber-based systems could scale to as many as 1,152 GPU packages, but final product names and configurations remain subject to change.

• Software and Full-Stack Optimization: CUDA remains central, with continued emphasis on vertical integration of hardware and software for maximum efficiency across training, post-training, inference, and agentic AI (via stacks like NemoClaw).

The platform advances every layer of the AI factory: compute, memory, storage, networking, and security.

Performance Expectations and Workload Focus

Exact performance numbers for Feynman GPUs are not yet public. However, the architectural shifts point to substantial gains:

• Dramatically higher compute density through 3D stacking and advanced nodes.
• Improved memory subsystem bandwidth and capacity.
• Much larger scalable systems enabled by optical interconnects (reducing power and latency penalties at scale).
• Better balance between training and inference, with LPUs handling latency-sensitive decode phases deterministically.
• Overall efficiency improvements critical for gigawatt-scale deployments.

NVIDIA positions these systems for the era of agentic AI-autonomous agents that reason, plan, and act-alongside traditional large language model workloads, robotics, and physical AI. The emphasis on deterministic execution and low-latency inference reflects a maturing AI industry moving from pure training scale to reliable, production-grade deployment.

Comparisons to Rubin suggest continued generational leaps similar to Blackwell’s improvements over Hopper, but with qualitative changes in interconnect technology and packaging that could enable entirely new system scales.

Uncertainties and What Remains Unknown

As of June 2026, Feynman is still in the design/validation phase (accelerated by Blackwell systems). Key unknowns include:

• Precise transistor counts, clock speeds, power consumption (TDP), and sustained performance metrics.
• Exact HBM configuration and whether multiple SKUs (e.g., a potential “Feynman Ultra”) will emerge.
• Final yield and cost implications of TSMC A16 + 3D stacking + custom packaging.
• Timeline risks-new process nodes and packaging technologies can face delays.
• Consumer/GeForce implications (if any)-Feynman appears firmly data-center focused initially, like Rubin.

NVIDIA has a strong track record of execution, but the complexity of these technologies means surprises are possible.

Broader Implications for AI and Computing

Feynman reinforces NVIDIA’s full-stack dominance in accelerated computing. By owning the CPU (Rosa), GPU (Feynman), specialized accelerators (LPUs), networking (BlueField, Spectrum, NVLink/CPO), and software (CUDA ecosystem), the company offers tightly optimized “AI factories” that are difficult for competitors to replicate piecemeal.

The shift to optical interconnects and 3D stacking could influence industry standards and supply chains (TSMC for leading-edge logic, memory makers for custom HBM, Intel for packaging elements). It also highlights the growing importance of inference-specific hardware alongside general-purpose GPUs.

For enterprises and hyperscalers, Feynman promises continued performance-per-watt and performance-per-dollar improvements at massive scale, enabling larger models, more agents, and new applications in robotics and beyond. However, it also deepens ecosystem lock-in through proprietary interconnects and optimized software stacks.

Conclusion: A Glimpse into the Next Era

The NVIDIA Feynman architecture represents more than an incremental upgrade-it embodies a strategic pivot toward vertically integrated, optically connected, 3D-stacked systems optimized for the full spectrum of future AI workloads. While detailed benchmarks and final specifications await silicon and system validation closer to 2028, the announced direction is bold and coherent: push manufacturing and packaging boundaries, embrace photonics to overcome interconnect limits, integrate specialized inference engines, and deliver full-stack platforms that scale to unprecedented levels.

Richard Feynman once emphasized understanding the world at its most fundamental levels. NVIDIA’s Feynman architecture applies that spirit to AI hardware-reaching “plenty of room at the bottom” through atomic-scale engineering and system-level innovation. As the industry races toward more capable, efficient, and ubiquitous AI, Feynman positions NVIDIA at the forefront of that transformation.

The coming years will reveal how well these ambitious plans translate into real-world silicon and deployed systems. For now, what we know paints a picture of continued leadership and exciting technological progress in accelerated computing.

Sources and Further Reading (links current as of research date):

• Wikipedia: Feynman (microarchitecture) - https://en.wikipedia.org/wiki/Feynman_(microarchitecture)
• Wccftech: NVIDIA Feynman GPU Gets 3D Die-Stacking, Custom HBM, & Next-Gen Rosa CPU - https://wccftech.com/nvidia-feynman-gpu-gets-3d-die-stacking-custom-hbm-next-gen-rosa-cpu/
• Wccftech: NVIDIA Unveils Next-Gen Feynman GPU In Updated Roadmap - https://wccftech.com/nvidia-next-gen-feynman-gpu-updated-roadmap-arriving-2028-next-gen-hbm-memory/
• Jon Peddie Research: Nvidia GTC 2026 keynote - https://www.jonpeddie.com/news/nvidia-gtc-2026-keynote/
• NVIDIA Blog: GTC 2026 Live Updates - https://blogs.nvidia.com/blog/gtc-2026-news/
• Tom’s Hardware: Nvidia updates data center roadmap with Rosa CPU and stacked Feynman GPUs - https://www.tomshardware.com/pc-components/gpus/nvidia-updates-data-center-roadmap-with-rosa-cpu-and-stacked-feynman-gpus-optical-nvlink-groq-lpus-with-nvfp4-and-nvlink-also-on-deck
• Counterpoint Research: From Blackwell to Feynman: Analyzing NVIDIA’s Optics Roadmap - https://counterpointresearch.com/en/insights/from-blackwell-to-feynman-analyzing-nvidias-optics-roadmap
• SemiAnalysis and other technical analyses referenced in coverage.
• Additional context from NVIDIA developer resources and GTC keynotes (available on NVIDIA’s site and YouTube).

This synthesis draws exclusively from publicly available authoritative reporting and official statements. As more details emerge from future GTC events or product launches, the picture will sharpen considerably.