Rate my daily 9900X 4-DIMM timings. Can we push subtimings further on mixed batches?
Hey boys, looking for some brutal honesty from the hardcore crowd. Trying to see if there is any more juice left to squeeze out of this AM5 4-DIMM daily gaming rig, or if I'm already hitting the physical limit of the memory controller.
Specs & Voltages:
- CPU: Ryzen 9 9900X (Dual-CCD)
- Mobo: ASRock X870 Steel Legend WiFi (BIOS 4.03)
- RAM: 4x16GB TeamGroup 6000Mhz CL30 Hynix M-die (4.D)
- VSOC: 1.280V fixed (Trying to keep the IMC alive long-term)
- VDD/VDDQ: 1.400V
The Catch:
These aren't a matched 4-stick kit. They are two completely separate retail kits manufactured 16 weeks apart (Week 3 and Week 19) with totally mixed wafer IDs and chaotic serials.
Current Timings (6000 MT/s 1:1 UCLK/MCLK, CR1):
Currently sitting at 6000 CL30-36-36-76 1:1 with FCLK locked at 2000. It already passed 6+ hours of TestMem5 Anta777 errorless, and has been a rock-solid daily runner for months with zero degradation.
My Question to the Experts:
Considering the massive capacitive and inductive load of this mixed 4-DIMM 2DPC setup, can I safely tighten tRFC, tREFI, tWR, or tRDRD/tWRWR subtimings further at 1.28V VSOC? Or should I leave it alone before the signal integrity collapses?
