How to properly discharge the capacitors of a DC/DC switching circuit after primary supply voltage has been switched off?
I am designing a DC/DC switching circuit based on TI's TPS62136 which steps down 12.5V-14.5V DC input to 11.6-ish V output. Figure 1 shows the schematics.
The primary supply voltage is hot-plugged to the input. The load is not a resistive load, but requires a forward voltage around 9-ish V, i.e. at some point during ramp-up/ramp-down of the secondary side the load becomes conductive/non-conductive.
As all specimen of my first attempt failed miserably during the 2nd power-cycle, I got a lot of helpful suggestions on this sub-reddit what I could improve.
One of the advices has been to considerably decrease the resistance of the voltage dividers (R1+R2 and R3+R4) to provide a safe path for the input/output capacitors to discharge when there is no input power. The advice pointed out that without an alternative path the capacitors might discharge trough the IC and destroy it.
While I decreased the total resistance of the voltage dividers significantly, the result isn't as expected. (TI's original reference design uses voltage dividers in the mega ohms, now it's only kilo ohms.) Here are the two main issues:
- There is indeed a reverse current around 100mA through the SW pin of the IC when being power-off which is responsible for the bulk of discharging the output capacitors.
- The input side still remains energized for quite a long time, as the time constant is approximately τ ≅ 450ms. (Note, the derated capacitance due to the DC bias is about 99µF not 2×47µF + 2×10µF = 114µF.)
Figure 2 shows the voltages: At 10.2ms the input supply is switched-off. Vic and Vout drop rapidly until Vic reaches 10.9V, then the IC switches off as EN drops below its 0.7V reference voltage. From there on, Vout smoothly decreases, i.e. C6+C7 are discharged, but Vic remains high.
Figure 3 shows some relevant currents: i(R503) (blue) is the current through the SW pin of the IC, i(V1) (orange) is the current through the simulated voltage supply and i(R204) (red) is the simulated load. At 10.2ms the current through i(V1) and i(R204) drops to zero, but one can see a reverse current of -100ms trough i(R503), i.e. the SW pin.
Here are my questions:
- Should I be worried about the -100ms reverse current through SW and should I do something about it? Are reverse currents a problem after all? The data sheet doesn't say anything about it. The data sheet neither warns about it nor explicitly states that it is fine. However, I wonder if it was an issues and had the potential to destroy the IC, I would have assumed that more people would report problems and there would be a warning. However, it could explain why my first batch failed on the 2nd power cycle.
- Should I be worried that Vic and the IC remain high and powered for quite some time? I cannot decrease the voltage divider any further without sacrificing efficiency and getting close to the maximum power rating of the resistors.
- Is there any better suited and recommended option to properly de-energize the circuit (input and output capacitors) during power off? My thoughts went into a direction of using MOSFETs of depletion type which are self-conductive and then construct something in the spirit of the slow-start mechanism which works the opposite way and shortens Vic/Vout to GND via a resistor with about 100Ω. But that was just a spontaneous idea. Probably there is something better. However, if possible I would like to keep it simply and not add more complexity to the circuit, if it isn't necessary.