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u/Boring_Ratio_4119

▲ 1 r/aggies

MS Course Regiration

I have a question regarding the course registration process for the Master of Science program. My undergraduate program uses a quarter-based system, and I’m current on my senior year, which resulted in my final-quarter transcript arriving later than in the semester-based system. However, as I looked at the courses I want to take during the Autumn semester, it seems like most courses are about to run out of spots. My current course registration status remains on hold due to the final-quarter transcript. Are there ways to solve this problem? Will the professor usually give out additional code for grad students' courses?

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u/Boring_Ratio_4119 — 4 days ago
▲ 49 r/PrintedCircuitBoard

Review Request: Controllable Feedback/Feedforward Loop Board

Hi everyone, I posted here a while ago to receive reviews for my schematic, and I’ve finally completed my layout. Here is a brief overview of my project. I’m implementing a programmable feedback and feedforward control loop that takes in a 0.3V to +0.3V signal and amplifies it to 15V, while performing stability control within the STMG4 MCU.

Here are some of the current functionalities

  • Voltage shifter at the input stage of the PGA and ADC, shifting the input to a common mode voltage of 1.65V.
  • Two different amplifiers are connected in a summing amplifier topology, which adds the feedforward and feedback paths (FB_OUT and FF_OUT). 
  • Other common microcontroller peripherals (NRST button, crystal oscillator, USB, LDO, decoupling capacitors for supplies,. etc).

I’m using a Signal - GND - GND - Signal stackup, while routing my power (5V, 18V, +18V, and 3V3) on the top and bottom signal layers. While adding stitching vias to stitch the ground planes together.

However, I have identified some concerns in my current design. 

  • One of my op amps does not have a solid ground below (two vias interrupting the solid ground plane)
  • I’ve chosen my ADC input resistor value based on the DS12288 manual, which shows the maximum resistance for a given sampling rate. I also added another capacitor to the ADC input stage for compensation.
  • I’m worried that some of the power traces aren't thick enough, and I'm considering dedicating power layers (switching to a 6-layer stack-up).

 

Any feedback and responses to this design are welcome!

u/Boring_Ratio_4119 — 14 days ago