u/DueKnowledge699

▲ 2 r/FPGA

Adding device tree also verify

Hi everyone,

I need to add this inside zynq-zed-adv7511-ad485x.dtsi

axi_dmac_event: dmac@43E10000 {

compatible = "adi,axi-dmac-1.00.a";

reg = <0x43E10000 0x1000>;

#dma-cells = <1>;

interrupt-parent = <&intc>;

interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clkc 15>;

adi,channels {

#size-cells = <0>;

#address-cells = <1>;

ae_event_dma_channel: dma-channel@0 {

reg = <0>;

adi,source-bus-type = <1>; /* 1 = AXI-Stream slave */

adi,source-bus-width = <16>;

adi,destination-bus-type = <0>; /* 0 = AXI-MM master */

adi,destination-bus-width = <64>;

};

};

};

Also I am using kuiper linux how can I verify? Can anyone help me out.

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u/DueKnowledge699 — 3 days ago
▲ 3 r/FPGA

FPGA Event Capture to DDR Integration Guidance

Hi everyone,

I’m working on an FPGA event capture system using ADI HDL + Kuiper Linux. I’m trying to store trigger-based waveform data into DDR using AXI DMAC, but I’m stuck on the integration architecture and DMA flow.

Since you’ve worked on similar systems before, could you guide me on the correct approach or best practices?

I’d really appreciate it.

Thank you.

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u/DueKnowledge699 — 10 days ago
▲ 1 r/FPGA

Hi all,

I am working on the DAQ system using eval board AD4857 + zedboard. Also I am using an ADI reference design. But now I need to use my custom design like event based data capture. What can I do? Can you help me out or just guide me .

Thank you.

Owais

reddit.com
u/DueKnowledge699 — 24 days ago