u/Glittering-Skirt-816

Hello,

I’m currently working on a Yocto + meta-xilinx workflow for Zynq UltraScale+ and I’m wondering if my workflow is completely wrong… or if everyone suffers the same way

My current workflow

1. Vivado

- make PL changes

- integrate Verilog into a custom IP

- add it to the Block Design

- validate BD

- run synthesis

- run implementation

-generate .xsa

2. Yocto / meta-xilinx

generate the SDT (`sdtgen`)

generate machine conf (`gen-machine-conf`)

run bitbake

flash SD card with dd

Total time: easily 30+ minutes for every small hardware change.

And very often I only discover stupid mistakes at runtime…

Example from today:

I forgot to reconnect an AXI slave.

No Vivado errors.

Yocto build succeeds.

Linux boots fine.

Then my app starts and obviously cannot find the AXI slave address...

So I have to redo everything just because of one missing AXI slave connection.

Questions :

How do you guys iterate faster with Yocto + meta-xilinx?

Some ideas I’ve been thinking about:

avoid rebuilding the full OS for every .xsa ? Is it possible ?

load only a new bitstream?

device tree overlays? I know that exists but don't know if it is usefull here

What the purpose of the fpga-manager ?

Thanks

Hey,

I fell while climbing around 3 weeks ago (I'm a regular; I've been doing this for 10 years) and hurt the area between my neck and shoulder / back of the shoulder.

At first the pain was pretty strong, now it’s mild (1–2/10) but still there with certain movements and especially in the morning or when I’m cold. Once I warm up and move around, it feels much better.

Doctor thinks it’s mostly muscular with maybe slight tendon involvement. I’m getting an ultrasound soon. He said I can slowly return to climbing if I stay reasonable.

For people who had something similar:

• How long did recovery take?
• Did movement help or did you rest completely?
• What helped the most?
• Did returning too early make it worse?

Thanks, I can't stand waiting any longer :|