u/Gundam_boogie_359 — reddlx

Where am I going wrong with this SMA to microstrip transition

I am working on an SMA to microstrip transition using OSHpark's 4 layer stack up. I am on my 2nd revision and do RF in my free time because I am trying to learn (I am an FPGA engineer).

I got my newest revision back and I was not very pleased. My physical boards are not matching my simulation very well at all.

I have compiled screenshots of my HFSS model, PCBs, SMA footprint, and NanoVNA results here: SMA Launch OSHpark 4 Layer - Imgur. The transition starts out as GCPW and runs the length of the signal pin pad. It then moves to a microstrip (no taper).

I simulated with HFSS using PEC, Isola FR408HR (in HFSS material library) and the nominal measurements from OSHpark's 4 layer stackup: OSH Park Docs ~ Services ~ 4 Layer Prototype Service . I also used the actual Samtec SMA connector HFSS encrypted model. I am learning a little about TDR and that looked okay in simulation, as well as S21 and S11. Due to using the student version and mesh limit, I can only simulate a 3mm long microstrip and I cannot model the solder connection from signal pin to pad.

I built two boards:

One with SMA launches on either side connected by a 1 inch and 2 inch microstrip (to calculate trace loss). I simulated the microstrip width in a separate HFSS sim (rough numbers calculated with SaturnPCB toolkit and revised/simulated from there).

The 2nd board is the SMA launch to a 4mm microstrip, then terminated with a 50 ohm, 0201 sized High Frequency resistor: TNPR020150R0FEED Vishay | Chip Resistor - Surface Mount | DigiKey

My actual PCB launch S11 is around -17 to -18 dB at 2.5 GHz, and around -10 dB at 6 GHz. I want to use this for the 2.4 and 5.8 GHz ISM bands. S21 is okay when I subtract my trace loss at 2.4 GHz, but gets a little wacky at 6 GHz (see imgur link S21 trace).

Is something off in my simulation? Should I use a different substrate than the one in the HFSS library? Could this be due to OSHpark manufacturing tolerances? I triple checked my dimensions for the footprint with the HFSS model and I dont think that could be the case unless they vary a lot once etched.

Any help would be appreciated! Thanks in advance.

u/Gundam_boogie_359 — 4 days ago

▲ 9 r/FPGA

11 ns reset pulse assertion

I have a reset signal that comes into my FPGA from an external source. It can vary in the time that it is asserted and has a minimum assertion time of 11 ns.

I am trying to do an analysis of if this minium assertion time is too short for my reset synchronizer.

This reset (rst_pulse) goes into the CLR inputs of a two flip flop reset synchronizer so it can be deasserted synchronously (it asserts asynchronously). The data output of the 2nd flip flop is used as the internal reset signal for the rest of the logic (standard reset synchronizer circuit). Therefore, rst_pulse only goes to two flip flops.

The FPGA is <100k logic elements and clock frequency for the reset synchronizer is < 40 MHz

I constrained the synchronizer flip flops to be as far away from the rst_pulse as possible in the device. Worst case net delay across all corners is < 4 ns. I have the freedom in the design to place the synchronizer anywhere, I just wanted to see what worst case delay would look like.

How would I move forward with deciding if the 11 ns assertion is too short? Since it is more than double my max net delay (which I can make shorter with constraints), does this mean it is okay?

I have done a little research and I think something else to consider would be recovery time? If anyone has a good paper on this which applies to my situation I would like to read it please.

Thank you!!!

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u/Gundam_boogie_359 — 1 month ago

▲ 27 r/rfelectronics

I am working on a VCO with a gain block for an FMCW radar. My schematic is shown in the 2nd pic. The output power of the 2.4 GHz VCO IC (MAX2750) is -3dBm. The gain block IC (QPA4563C) has a gain of 19.8 dB and OP1dB of 14.6 @ 2.4 GHz. This is my first active RF circuit, and I wasnt sure what running the gain block in saturation would do so I added a 3dB attenuator to the output of the VCO.

In my mind, this attenuated the VCO output to -6 dB. Then with 19.8 dB of gain from the amp, I wouldn't be running the amp in saturation (total output power of 13.8 dB -- maybe this would be considered compression?).

The part number of the attenuator is TFA20C03DBER. I used the footprint from the datasheet. When I first built the entire board last night, I got a total output power of -25 dBm! I was expecting around 12 dBm. After a few hours debugging today, I ended up removing the attenuator and just shorting the trace. This resulted in an output power of 12 dBm as expected. The spectrum without the 3dB attenuator is shown in the last slide (has an external 20dB attenuator on the analyzer).

Where did I go wrong with the 3dB attenuator? I tried another one also and flipped it around but no luck. The only thing that worked was removing it and shorting the trace.

Also for my spectrum analyzer output, why are all the peaks separated by 10 MHz? I tested phase noise and got what I expected from the VCO, just not sure if something like this is normal?

u/Gundam_boogie_359 — 4 months ago