u/Inevitable_Lie6006

Hey guys, I recently graduated with a Master's in Computer Engineering. I have academic projects in UVM and SystemVerilog, but honestly, none of them seem to be gaining any traction with recruiters.

Looking for advice on two things:

1. Projects – What kind of projects should I add to my profile to better target Design Verification and RTL Design roles? Are there specific protocols, tools, or complexity levels that stand out?
2. Practice problem writeups – Is it worth adding my solutions to SystemVerilog constraint problems, simple UART verification environments, LeetSilicon problems, etc. to my GitHub/portfolio? Or does that come across as filler?

And to my fellow peers who landed a job, especially without prior relevant industry experience — what's the one thing you think helped you stand out when everyone around you had the same academic projects?

Appreciate any honest feedback. It's a tough market out there and I want to make sure I'm spending my time on the right things.

I’ve been applying for around 6 months now and struggling to get callbacks despite having projects in UVM/SystemVerilog, RTL design, and FPGA/embedded systems. I’d really appreciate feedback from people in the VLSI industry on whether:

• my resume presentation is hurting me,
• my projects aren’t aligned enough with current hiring,
• or if this is largely due to the current entry-level market.

Would genuinely appreciate any honest feedback or suggestions for improving my profile/job search strategy.

(Resume attached)

https://preview.redd.it/6gsx9gxoor0h1.jpg?width=2550&format=pjpg&auto=webp&s=949a91dc86a28976b4486a33697b852d88265c03

Hey everyone,

I recently graduated with a Master’s in Computer Engineering and have been actively applying for full-time roles over the past 6 months, primarily in ASIC/verification-related positions.

I wanted to ask for some honest advice from people in the industry. I’m applying consistently, reaching out for referrals, networking on LinkedIn, and tailoring applications where I can, but I’m still struggling to get callbacks.

At this point, I’m trying to understand where the gap might be:

• Resume?
• Experience/projects?
• Application strategy?
• Market conditions?
• Something else I may be overlooking?

I’m not posting this to complain, just genuinely trying to learn and improve my approach. If anyone has pointers, feedback, or insights from their own experience navigating the current job market, I’d really appreciate it.

https://preview.redd.it/zk55montjr0h1.jpg?width=2550&format=pjpg&auto=webp&s=92ff33a8d9db2c56d8113f16e63f7c343f0b195a

Thank you.

Hi r/chipdesign,

Graduating May 2026 (NCSU, MS Computer Engineering) and targeting Design Verification / SoC Verification roles. Aiming for companies like ARM, Qualcomm, NVIDIA, Apple, Synopsys. I've been job hunting for a while now and the silence has been deafening.

My verification experience is almost entirely project-based (UVM testbench for LC3 microcontroller end-to-end, I2C multi-bus controller verification, OOO processor simulator in C++). I have solid coursework in UVM and ASIC verification.

What I'm unsure about:

- My full-time job title says "Software Developer" at an MNC, I was supporting EDA/hardware teams, but I worry the title alone makes me look like a software person who pivoted

- Do my project bullets read like someone who actually understands verification, or do they sound like coursework padding?

- Is there anything in the framing or ordering that would make a DV hiring manager skip me?

Happy to hear brutal feedback. Also open to DMs if you're hiring new-grad verification engineers or know teams that are.

https://preview.redd.it/6f08j5y8yxzg1.jpg?width=2550&format=pjpg&auto=webp&s=33fa53eaa2ab534d3fd20d330bf2e8bd5f150e0c