>Marvell Technology ​said on Wednesday it has ‌issued Alphabet's Google a warrant to buy a stake worth about $12.18 billion as ​part of a deal to ​help develop custom chips for the ⁠search giant. Shares of the custom ​chipmaker jumped more than 11% in ​premarket trading, while larger rival Broadcom was down over 3%.

>Demand for custom chips such ​as Google's tensor processing units (TPUs), ​used for AI workloads, has surged in recent ‌years ⁠as businesses seek alternatives to Nvidia's pricey graphics processors.

>Marvell said it would develop AI inference accelerators, storage, ​networking and ​memory ⁠interface controllers and near-memory computing technologies for Google.

>In April, ​Broadcom signed a long-term agreement with ​Google ⁠to develop and supply future generations of custom AI chips and ⁠other ​components for the company's ​next-generation AI racks through 2031.

Positive signs for MU/memory as DRAM and HBM is needed for Google's growing TPU ecosystem too - MRVL design the physical onboard controllers for their chips which need memory and they work with MU as one of their close business partners to do this: Source (Reuters)

TrendForce’s latest NAND Flash industry research reveals that AI server demand remained steady in the second quarter of 2026—particularly for enterprise SSDs—resulting in a supply shortage across the NAND Flash market. This allowed suppliers to raise ASPs significantly through contract negotiations. As a result, the combined revenue of the top five publicly listed NAND Flash brands rose 77% QoQ to US$68.87 billion.

Looking ahead to the third quarter, demand from smartphones and PCs is expected to remain weak as higher BOM costs push up device prices. However, demand from AI servers for enterprise SSDs remains strong. Meanwhile, suppliers are generally prioritizing capital expenditure on DRAM and HBM, limiting new NAND Flash capacity. ASPs are therefore expected to continue supporting overall industry revenue growth in the third quarter.

Among the top five NAND Flash brands, market leader Samsung benefited from higher NAND Flash ASPs driven by AI server demand, while a growing share of enterprise SSD shipments significantly improved profitability. Revenue rose 70.7% QoQ to nearly $23.06 billion. However, as competitors posted faster revenue growth, Samsung’s market share edged down to 29.3% in the second quarter.

SK hynix Group, including SK hynix and Solidigm, ranked second. Continued ramp-up of its 321-layer process, strong orders for Solidigm’s high-capacity QLC enterprise SSDs, and rising ASPs lifted NAND Flash revenue 89.5% QoQ to more than $14.27 billion. Its operating margin also reached another record high.

>Micron likewise benefited from a significant increase in ASPs, with NAND Flash revenue reaching $11.85 billion, up 99.2% QoQ — the highest growth rate among the top five brands. This lifted Micron to third place.

Kioxia ranked fourth. Revenue and profitability increased, supported by persistently high NAND Flash prices and continued growth in BiCS8 output. Revenue rose 79.9% QoQ to approximately $10.72 billion, while market share edged down to 13.6%.

SanDisk also benefited from AI-driven ASP increases in the second quarter. However, relatively conservative bit shipment growth limited its revenue increase to 50.7% QoQ, reaching nearly $8.97 billion and trailing the growth of its peers.

Original source (no paywall)

SK hynix is reportedly strengthening its HBM co-design capabilities in Silicon Valley as it deepens collaboration with global Big Tech customers. According to NewsPim, sources say SK hynix America operates an HBM Architect Design Team in San Jose, California, working directly with major U.S. customers on base-die design for HBM and 3D-stacked DRAM. The team develops next-generation HBM architectures around customer requirements, going beyond local technical support to collaborate throughout product development.

Notably, NewsPim adds that SK hynix is expanding the team, offering annual salaries of US$150,000–US$260,000. The company is seeking experience in DRAM and HBM architecture, full-custom and digital co-design, power delivery network (PDN) analysis, and logic foundry design, with experience in 1x-nanometer DRAM and foundry nodes of 3nm or below preferred. Developing advanced, customer-tailored HBM architectures for future products is among the team’s core responsibilities, the report notes.

The San Jose location also supports this strategy. As NewsPim notes, NVIDIA and AMD are headquartered in nearby Santa Clara, while Broadcom has operations in San Jose. Positioning HBM engineers near these major AI chip design hubs allows SK hynix to work directly with customers on next-generation products and quickly relay their requirements to development teams in South Korea.

SK hynix is already deepening such collaboration with NVIDIA. Chosun Ilbo notes that the two companies are jointly developing next-generation memory for AI factories, expanding their partnership beyond supplying existing HBM toward developing advanced memory aligned with NVIDIA’s next-generation roadmap.

Customer Co-Design Reshapes HBM Competition

Customer co-design is expected to become even more important with HBM4 and future generations. As NewsPim notes, increasingly diverse AI accelerator architectures are driving different requirements for HBM capacity, bandwidth, and power, making early co-optimization of AI chips and memory increasingly important.

This is also reshaping HBM competition. Memory suppliers that participate early in customers’ next-generation AI chip development can incorporate specific requirements into their designs, while co-developed HBM may raise barriers for rivals seeking to enter the same supply chain later. As the report points out, such collaboration is becoming increasingly important for securing next-generation HBM orders.

The trend extends beyond SK hynix. Seoul Economic Daily notes that Samsung is recruiting base-die designers as customer-specific optimization for AI accelerator vendors becomes increasingly important with HBM4. The company is also hiring application engineers to evaluate HBM on AI accelerator systems and support key customer qualifications, with the aim of shortening the certification process.

Original source (Trendforce)

Lam Research Corp announced that it intends to invest more than $3 billion over the next five years to expand its global research and development (R&D) lab network. The planned multi-site expansion is expected to add infrastructure and capabilities to increase experiment capacity by more than 50%. Lam's R&D approach combines specialized labs worldwide, each purpose-built to accelerate a distinct step of the innovation cycle, with deep customer collaboration that includes locations near customer facilities. Together, Lam's labs operate as an integrated 24/7 network, enabling innovation in parallel and at scale. With this investment, Lam intends to further compress product development cycles for customers, from pathfinding to fab deployment.

>"In the AI era, the pace of innovation is relentless, requiring chips with new architectures, different materials, and complex features engineered with nanoscale precision. Our ability to increase velocity throughout the R&D process has become a decisive advantage," said Tim Archer, president and chief executive officer of Lam Research. "We are investing with the intention of staying ahead of what our customers need, further strengthening our global innovation engine to deliver the next generation of semiconductor breakthroughs."

Lam's global lab network spans the United States, Asia, and Europe. The combined R&D infrastructure supports more than one million experiments annually. Facilities specialized for foundational research in new chemistries, materials and mechatronics have the capability to compress weeks of experimental work into as little as a few days in many cases. Process development labs carry those advances toward production readiness, with engineering, product development and manufacturing teams working side by side on the same tools. Located in proximity to customers, Lam's technology centers support rapid qualification and validation alongside customers' engineering teams.

The integrated lab network enables tools, data and expertise to be shared across locations and time zones, so a discovery in one lab becomes knowledge every lab can use. In recent customer engagements, this approach has enabled Lam to shorten process development up to 2.5 times.

>"Congratulations to Lam on this investment. Micron is proud to work with Lam as we advance memory and storage solutions that power the AI ecosystem," said Scott DeBoer, executive vice president and chief technology and products officer at Micron Technology. "Our longstanding collaboration with Lam continues to drive innovation in leading-edge front-end and advanced packaging technologies, and we look forward to building on this momentum to scale AI across the semiconductor ecosystem."

Lam plans to begin expanding the global lab network this year with the goal of increasing innovation velocity.

Lam Research is one of MU's most important, closest, longstanding US-based business partners and fab equipment suppliers (they even opened a new office this year in Boise close to MU's HQ) - Full article

NAND shortages are intensifying as Phison warns that it will take years to catch up to demand, signaling a rise in SSD prices.

According to Phison CEO Pua Khein-Seng, it is said that the NAND production capacity cannot meet demand in the short term. The company is building up a "strategic' inventory to ensure a stable supply of Enterprise SSDs for CSPs and AI firms for the next two years, but the demand is so high that it will take years for production to catch up.

>Phison's CEO states that while the impression in the market is that manufacturers can easily build & expand new production capacity, the reality is that the time required to set up new production is much longer. NAND manufacturers told Cheng that even the two-year timeline was ambitious, and it would actually take around four years to set up new production capacity.

>Pua Khein-Seng stated that the market often believes that after memory prices rise, manufacturers can quickly increase capital expenditures and expand production capacity, but in reality, the time required to add new NAND production capacity is much longer than the market imagines.

>He revealed that during a recent exchange with senior executives of the NAND manufacturer, he asked how long it would take from investment to actual mass production. He originally estimated it would take about two years, but the answer they gave was "four years". - Commercial Times

As such, the current estimation is that NAND shortages will persist for at least four years from now, and during this period, NAND prices will increase substantially as demand continues to grow. Phison will hold back from selling a large amount of its inventory as part of its "strategic" inventory since it will be unable to obtain a sufficient supply in the future, affecting its "long-term" partnerships.

To make matters worse, while AI firms and cloud providers are adjusting their DRAM specs, NAND capacity has not decreased that much, which highlights the importance of storage in the AI era. The rise of Agentic AI and GenAI use cases requires large amounts of data to be stored in the cloud, which means that more storage capacity is required.

For those not already aware, Phison design SSD controllers for Micron and Kioxia as well - Full article

Original source (Chinese)

>Such is the scale of NVIDIA's ongoing production ramp-up for its Vera Rubin platform that it's now manifesting itself in seemingly sparsely related nooks and cranies of the supply chain, such as the spot market for TLC NAND.

>In hindsight though, the rise in spot TLC prices is entirely reasonable, especially given the Context Memory eXtension (CMX) that NVIDIA is bringing onboard with the Vera Rubin platform.

>NVIDIA's production ramp-up of its Vera Rubin platform is squeezing TLC NAND supply by locking in a growing number of NAND cells within the CMX, and as enterprise SSD demand scales up in tandem. The spot price of a 512Gb TLC NAND has now hit $21 after falling below this level in June. And, there are a number of factors contributing to this renewed inflationary impulse.

>First, to handle the KV cache - the notes created by an AI model's attention layers as they form connections between words in a given input prompt - NVIDIA is introducing Context Memory eXtension (CMX) within the Vera Rubin platform.

>The CMX creates an intermediate storage tier between the HBM and the traditional backend network storage, functioning as a massive pool of TLC flash memory that is attached to the Rubin GPU cluster using NVIDIA BlueField-4 DPUs - that act as the 'intelligent brain' for a CMX server to handle KV cache in real-time - over ultra-fast Spectrum-X Ethernet.

>In fact, a single 2U CMX server holds 600TB of TLC flash storage, with each of the four DPUs managing 150TB of context memory, with pod-level capacity hitting a massive 9,600 TB or 9.6 Perabytes!

>Second, data centers require high-density, high-performance Enterprise SSDs (eSSDs) to handle AI workloads. And, as Vera Rubin ramps up, so does the demand for these eSSDs.

>Of course, do note that much of the TLC NAND that NVIDIA is now consuming is likely locked behind long-term contracts. Even so, the sheer scale of the oncoming demand is now tightening the spot market as well, and it remains to be seen how far this trend will go.

More good signs for SK's NAND demand/pricing power.

Full article (no paywall)

Goldman Sachs is in talks with potential investors about participating in Nvidia's $500 billion ​AI financing initiative, after leveraging its long-standing relationship with the chipmaker to secure a coveted role in the deal, people familiar with ‌the matter said.

U.S. insurers, money managers and banks are expected to form the core investor base for the financing, one of the people said, while asset managers plan to retain a sizable share of the financing, a second source said.

Nvidia announced on August 10 it has partnered with six major financial institutions including Goldman to launch compute platforms aimed at raising over $500 billion in third-party ​capital for AI infrastructure. The move highlights how surging demand for AI computing capacity is drawing institutional investors, as governments, companies and startups race to ​build out data centers to support AI workloads.

Goldman can provide junior capital and private credit financing through its asset management ⁠arm, while its investment bank can also help place the debt into private credit funds and eventually public debt markets, the second source said.

The first source said ​the firm had held discussions with a wide range of investors about such structures, including banks, asset managers, insurers and private credit firms.

The Wall Street bank's central role ​as the sole lender on the deal, alongside alternative asset management giants such as Blackstone and Apollo, marks the culmination of years of ties with Nvidia.

Goldman Sachs has advised Nvidia on several transactions and on numerous technology financing deals in which the chipmaker was an investor, according to Dealogic. The bank was also among the lead underwriters on the chipmaker's $25 billion bond sale ​in June and served as an exclusive financial adviser on Nvidia's $6.9 billion acquisition of Mellanox Technologies in 2019.

The bank's technology teams also maintain close ties with Nvidia, ​while the relationship extends to the highest levels of both companies, the second source and a third source familiar with the matter said. Less than two years ago, Goldman Sachs CEO ‌David Solomon ⁠interviewed Nvidia CEO Jensen Huang at a technology conference hosted by the Wall Street firm.

"Jensen came, approached us with the idea, and we said we'd love to talk to you about it," Solomon told CNBC in a joint interview with Huang and executives of other partner firms after the Nvidia financing plan was unveiled on Monday.

More market positivity and good news for semis and SK - Full article (no paywall)

>Samsung and SK hynix are accelerating the adoption of artificial intelligence (AI) agents in semiconductor manufacturing equipment. According to The Elec, SK hynix has begun a phased deployment of AI agents across its back-end production lines in Cheongju, though the specific equipment involved has not been disclosed. The company is evaluating equipment performance as well as the effectiveness and reliability of AI agent functions in production environments, with testing expected to conclude by year-end. SK hynix ultimately aims to establish autonomous semiconductor manufacturing facilities by 2030.

>SK hynix has reportedly tied the KPIs of employees responsible for equipment qualification to the successful validation and deployment of AI software. AI-driven improvements in production yield are also reflected in their performance evaluations.

>As the report indicates, SK hynix Executive Vice President Do Seung-yong stressed the growing importance of AI-driven manufacturing, noting that surging memory demand cannot be addressed through fab expansion alone. AI can enable more sophisticated decision-making across quality, cost, and production speed than conventional rule-based automation.

>SK hynix is also expanding the infrastructure needed to support these efforts. According to another report from The Elec, sources say the company will install 250 AI servers equipped with 2,000 NVIDIA Blackwell GPUs at its Cheongju campus, marking its first direct deployment of a standalone AI system at a production site. The infrastructure will support factory digital twins and internal AI agents as semiconductor manufacturing moves toward AI-operated fabs.

Good to see semis are adopting more AI in their manufacturing process which potentially scales up even their own memory usage and demand to keep up.

Full article (no paywall)

>TSMC reportedly has a large stockpile of Apple chips as the company waits for DRAM delivery from Apple's suppliers to integrate into a complete package. Using Integrated Fan-Out Package on Package (InFO-PoP), TSMC is developing a 3D wafer-level fan-out package. This package is designed to hold memory directly above the SoC die, resulting in a smaller PCB design without the LPDDR5X module occupying over 100 mm² of PCB area. With less than six weeks until the launch of the iPhone 18 series and the iPhone Ultra, Apple is rushing to place DRAM orders to secure new supplies. The Cupertino-based giant primarily relies on DRAM from Micron, whose LPDDR5X memory is used in a range of devices and is the main source for the next-generation iPhone. SK hynix and Samsung are also suppliers, but Micron remains the primary choice.

>Apple has reportedly been working to get more manufacturers on board, even negotiating with CXMT for a discount based on volume, but CXMT reportedly rejected this idea. As TSMC waits for Apple's DRAM suppliers, especially Micron, the company can't assemble Apple's processors just yet. InFO-PoP requires DRAM dies to be integrated into the package, and TSMC can't ship any processors before packaging is complete. This process reportedly takes up to two weeks, which means that TSMC and Apple will be working with a tight deadline around the launch of the latest iPhone update.

Apple's upcoming iPhone 18 (which is launching in September) is running into production halts - a lot of their in-house A20 chips are waiting in the assembly line due to the ongoing DRAM sourcing problems.

Original article

Chinese memory manufacturer CXMT has refused Apple's demand for a price cut in negotiations, says a report from the Korean press. Apple has widely been reported to be interested in procuring its chips from CXMT and has purportedly lobbied the US government for the permission to purchase the products for its gadgets sold outside the country. However, the report from the Korean publication Digital Daily outlines that demand from Huawei, Xiaomi and others has placed CXMT in a stronger position to negotiate with the world's largest consumer electronics firm.

CXMT's Domestic Customers Provide It Leverage In Negotiations With Apple

According to the details, as CXMT has emerged to become one of the top players in China's memory market, Samsung and SK hynix have instead chosen to focus on manufacturing and selling high-value HBM memory chips catered to the needs of the data center industry. As a result, CXMT is experiencing high demand from domestic Chinese companies such as Huawei and Xiaomi, which have provided it with the leverage to bargain with Apple.

Sources quoted by Korea's Digital Daily outline that during its negotiations with CXMT, Apple asked for a price cut in order to ease pricing pressures for its smartphones and the upcoming 2026 iPhone. However, CXMT refused the price cut and instead quoted prices that were at level with or higher than the prices quoted by Samsung and SK hynix.

The publication adds that US sanctions on China have led Huawei, Xiaomi and others to lock in CXMT's DRAM memory output in advance. This lock-up is similar to the contracts that the Korean firms have utilized, and they are also high-priced agreements that prevent CXMT from yielding to Apple's requests. According to the sources, the higher prices have provided CXMT with the leverage to negotiate with Apple, as it can point towards the existing deals already in place.

Additionally, the higher prices have also removed a long-followed strategy in sourcing where device manufacturers would quote lower-priced Chinese inputs to use them as leverage in negotiations with other firms.

The higher domestic demand in China has also benefited Korean suppliers Samsung and SK hynix, as they are no longer required to be committed to delivering lower-priced commodity DRAM chips to Chinese firms. Instead, the firms can fully focus on the pricier HBM memory chips required for the AI infrastructure buildout. According to an industry official quoted by the publication, CXMT is effectively controlling the price floor of the commodity DRAM market.

Original source

>CoreWeave, the Essential Cloud for AI™, today announced a multi-year strategic agreement with Solidigm, a pioneer in enterprise data storage and a leading supplier of high-capacity AI infrastructure storage solutions, for priority access to enterprise solid-state drive (SSD) capacity supporting CoreWeave’s AI cloud platform. The agreement extends CoreWeave’s integrated approach to AI, helping to ensure that storage capacity scales alongside customer demand across the rest of its platform.

>AI workloads depend on an integrated stack – compute, networking, storage, and software – that performs together at scale. As demand for AI accelerates, keeping every layer of that stack ahead of demand has become essential to how quickly customers can move from experimentation to production. Storage, in particular, has become a critical constraint in capacity planning. CoreWeave established this direct, multi-year agreement with Solidigm to secure priority allocation as enterprise AI adoption accelerates and industry-wide storage supply tightens.

>"CoreWeave was built to give AI pioneers everything they need in one place, so they can build and deploy without stitching together their own infrastructure," said Sachin Jain, chief operating officer of CoreWeave. "Storage is part of that promise. This agreement gives us priority access to the storage our roadmap depends on, allowing customers to focus on what they’re building instead of the infrastructure underneath it."

>"Long-term supply commitments are becoming a strategic advantage of staying ahead of demand, and this agreement aligns to that vision," said Paul Palonsky, executive vice president and head of global sales at Solidigm. "This agreement reflects the confidence Solidigm has in CoreWeave's growth and its position as a full-stack AI cloud provider. "

>CoreWeave consistently delivers industry-leading performance, demonstrated by record-breaking MLPerf benchmark results, its position as the only AI cloud provider to earn the top Platinum ranking in both SemiAnalysis ClusterMAX™ 1.0 and 2.0, and its #1 ranking for inference speed and price-performance for Moonshot AI’s Kimi K2.6 in independent inference benchmarking conducted by Artificial Analysis.

About CoreWeave
CoreWeave is The Essential Cloud for AI™. Built for pioneers by pioneers, CoreWeave delivers a platform of technology, tools, and teams that enables innovators to move at the pace of innovation, building and scaling AI with confidence. Trusted by leading AI labs, startups, and global enterprises, CoreWeave serves as a force multiplier by combining superior infrastructure performance with deep technical expertise to accelerate breakthroughs. Established in 2017, CoreWeave completed its public listing on Nasdaq (CRWV) in March 2025. Learn more at www.coreweave.com.

About Solidigm
Solidigm, a pioneer in enterprise data storage, leverages decades of product leadership and technical innovation, collaborating with customers to transform their business and propel them into the data-centric future. Our legacy of industry leadership is helping enable AI and more with our robust end-to-end product portfolio for core data centers to the edge. Headquartered in Rancho Cordova, California, Solidigm operates globally as a standalone subsidiary of SK hynix Inc. Discover how we're advancing the industry at solidigm.com.

Original source

>cuFile is an open source component of NVIDIA GPUDirect Storage - Using hundreds of thousands of GPU threads, fast high-bandwidth memory and other methodologies, cuFile enables securely accessing data from storage in just microseconds.

>This represents how the industry is unifying a security-first storage stack based on Linux best practices, providing interoperability between GPUs and data. 

>In addition, fast, secure access to data and storage is a foundational element to powering preventive and detective cybersecurity measures. Making cuFile openly available will help make security context, data and storage accessible at the speed AI-powered defenses need. Such open technologies support initiatives such as the new Open Secure AI Alliance.

>This site is the new home for APIs that are open to contributions — with Google, Intel, NVIDIA and Meta as inaugural maintainers — and can be optimized for use across various software and hardware platforms, driving innovation and efficiency for developers and enterprises.

More innovation and performance coming from NVIDIA that was announced a moment ago today at the big FMS 2026 conference.

NVIDIA official blog

Surging investment in AI infrastructure is expected to drive the combined CapEx of the world’s nine largest CSPs up by approximately 90% YoY in 2026, according to TrendForce’s latest AI server research. 

Most recently, procurement demand for NVIDIA GB/VR rack-scale AI server platforms has strengthened noticeably among hyperscale CSPs and Tier-2 data center operators. Meanwhile, Google and AWS are set to ramp production of their next-gen in-house ASIC platforms during the second half of 2026, while Chinese CSPs are accelerating the deployment of domestic AI solutions to support LLM services. 

TrendForce has therefore revised its 2026 AI server shipment forecast upward from 28% to nearly 31% YoY.

TrendForce estimates that the combined 2026 CapEx of Google, Amazon, Meta, Microsoft, Oracle, ByteDance, Tencent, Alibaba, and Baidu will exceed US$886.7 billion, with the five North American hyperscalers accounting for nearly 90%. This increased spending reflects continued investment in AI data centers, GPU clusters, liquid-cooling infrastructure, and other next-generation AI infrastructure required to support the rapidly growing demand for generative AI and large-scale models.

Breaking down AI chip strategies among North American CSPs, TrendForce observes that Google remains focused on expanding the deployment of its in-house TPUs throughout 2026 and 2027, with shipments continuing to grow rapidly in 2027. AWS is expected to deploy NVIDIA GB300 as its primary GPU AI server platform in 2026 while steadily expanding shipments of its internally developed ASICs, with further volume growth anticipated in 2027. Meta will rely primarily on NVIDIA GB/VR and AMD Helios rack-scale systems in 2026, while significantly accelerating deployment of its proprietary AI ASICs in 2027 as part of its long-term strategy to reduce AI infrastructure costs and improve inference efficiency.

CapEx of China’s four largest CSPs expected to grow by more than 80% in 2026

Chinese CSPs are also entering a new investment cycle of AI infrastructure. TrendForce forecasts that the combined CapEx of ByteDance, Tencent, Alibaba, and Baidu will increase by more than 80% YoY in 2026. Among them, ByteDance is expected to post the largest increase, with investment focused primarily on large-scale AI data centers, proprietary ASIC development, and the deployment of GPU clusters.

Looking to 2027, TrendForce estimates that the combined CapEx of the top nine CSPs will hit about $1.3 trillion, showing nearly 50% year-over-year growth. While the growth rate may slow due to a higher comparison baseline, this does not suggest a decline in AI investments. 

Ongoing developments in AI inference, Agentic AI, custom ASICs, and next-generation AI models will keep fueling strong demand for computing infrastructure. As a result, CSP investments are likely to reach new record levels, expanding beyond GPU deployment to include upgrades across AI servers, liquid cooling, advanced packaging, high-speed interconnects, power infrastructure, and memory. 

Original source from Trendforce

Future of Memory and Storage Conference (FMS) – Kioxia Corporation, a subsidiary of Kioxia Holdings Corporation and Sandisk Corporation today unveiled their next-generation Quad-Level-Cell (QLC) 3D flash memory technology, which delivers up to 60% increase in bit density compared to their 8th-generation, surpassing 37 Gb/mm² and setting the industry benchmark^(1) for bit density, performance and power efficiency.

Leveraging the companies’ revolutionary CMOS directly Bonded to Array (CBA) technology^(2) which fabricates CMOS logic and the memory array on separate wafers before bonding them together with high-precision wafer-to-wafer alignment, the new generation improves read and write bandwidth compared to the 8th-generation 3D flash memory and becomes the industry’s first QLC 3D flash memory technology to reach a 4.8 Gb/s ^(3) interface.

Additional interface enhancements improve I/O data-out transfer power efficiency. These large power efficiency upgrades directly address the power and cooling challenges of modern AI and cloud infrastructure.

Chief Technology Officer at Kioxia, Hideshi Miyajima, said, “As AI continues to underpin the advancement of society, its applications are expanding from generative AI to agent-based and physical AI, while the use of data is becoming increasingly diverse and sophisticated. QLC technology enables the efficient storage of rapidly expanding data volumes, helping deliver greater performance and scalability for AI systems. Kioxia will accelerate development toward the commercialization of its 10th-generation flash memory products incorporating QLC technology.”

Chief Technology Officer at Sandisk, Alper Ilkbahar, said, "As AI training, inference, and hyperscale datacenter workloads drive unprecedented growth in data generation, the storage industry faces increasing pressure to deliver greater capacity, higher performance, and improved energy efficiency. By redefining the performance and efficiency envelope of QLC NAND, our 10th-generation QLC 3D flash memory delivers simultaneous gains in density, bandwidth, and energy efficiency and establishes a new paradigm for high‑capacity flash storage to provide a scalable foundation for next‑generation infrastructure applications.”

Key 10th-genaration QLC 3D flash memory technology highlights include:

• 332‑layer architecture and optimized floorplan design deliver up to 60% increase in bit density, achieving >37 Gb/mm² compared to the 8th-generation.
• 4.8 Gb/s ^(3) NAND interface enabled by Toggle DDR6.0 and the Separate Command Address (SCA) protocol to unlock the full potential of fast interface.
• CMOS directly Bonded to Array (CBA) architecture enhances density scaling, performance, and manufacturing efficiency.
• Power‑Isolated Low‑Tapped Termination (PI‑LTT) improves I/O data-out transfer power efficiency.

1. As of August 4, 2026, based on Kioxia and Sandisk survey.
2. Technology wherein each CMOS wafer and cell array wafer are manufactured separately in their optimized condition and then bonded together.
3. 1Gb/s is calculated as 1,000,000,000 bits/second. This value is obtained under our specific test environment, and may vary depending on use conditions.

Original source (no paywall)

Higher wafer and memory costs are beginning to push up graphics card prices. According to ZDNet, sources say prices for NVIDIA’s GeForce RTX 50 series graphics cards in South Korea could rise by as much as 30% this month. The report attributes the expected price increases to higher wafer and GDDR7 memory costs. TSMC announced in July that it would raise wafer prices for 7nm and more advanced processes. The GPUs are manufactured by TSMC on 4nm, as noted by Wccftech,

NVIDIA supplies RTX 50 series GPUs and GDDR memory to graphics card manufacturers as a bundled kit. As GDDR7 memory prices rise, kit costs increase accordingly, leaving manufacturers little choice but to pass the higher procurement costs on through product pricing, according to the report.

A representative from one manufacturer said major vendors temporarily halted shipments ahead of the August price increases, leaving few distributors able to secure inventory before the higher prices took effect, as noted by the report. Some manufacturers had already begun raising graphics card prices over the previous weekend, the report adds.

Higher-end models equipped with larger GDDR7 memory capacities have seen greater cost increases, the report notes. Depending on the manufacturer, flagship GeForce RTX 5090 (32GB) models have risen by as much as KRW 1.5 million since mid-July, with some now selling for around KRW 7.3 million.

Similar price increases have also been reflected in the U.S. and Chinese markets. According to a July report by Wccftech, GPU prices in China have climbed sharply following recent GDDR6 and GDDR7 memory price increases. The GeForce RTX 5090D 32GB has reportedly risen 22.5% from its previous price and now retails at more than twice its manufacturer’s suggested retail price (MSRP). Meanwhile, according to Tom’s Hardware, the Asus ROG Astral RTX 5080 is listed at US$2,099.99 at Best Buy, about US$600 above its launch MSRP.

Citing data from South Korean price comparison website Danawa, the report points out that the cheapest GeForce RTX 5060 Ti (8GB) model now sells for around KRW 700,000 (about US$490), roughly KRW 100,000 (about US$70) higher than before. Meanwhile, the lowest-priced GeForce RTX 5070 model is listed at around KRW 1.1 million (about US$770), up approximately KRW 200,000 (about US$140).

Full article (Trendforce - no paywall)

>While both Intel and SK hynix denied market chatters that the latter could work towards acquiring Team Blue’s Ohio fab, the two parties could still be exploring collaboration opportunities. Semafor, citing sources familiar with the matter, reports that SK hynix is among the potential partners being considered to help operate the facility, rather than take full ownership.

>As reported by Barron’s earlier, in a regulatory filing with the Korea Exchange on Wednesday, SK hynix reiterated that it “has not pursued or decided to acquire Intel’s Ohio site,” while adding that it continues to review a range of investment and acquisition opportunities.

>Discussions remain at an early stage, though. According to Semafor, Intel is seeking a partner to help advance its long-delayed Ohio semiconductor project, but the two companies have yet to begin formal negotiations over a potential operating arrangement. Another source close to Intel described SK hynix’s interest as preliminary.

>Notably, Economy Tribune suggests that Intel has prior experience using external capital while retaining fab ownership and operational control. In 2022, the company partnered with Brookfield on a Semiconductor Co-Investment Program (SCIP), jointly investing up to US$30 billion in its Arizona Ocotillo campus, with Intel holding a 51% stake and Brookfield 49%, the report adds.

>Economy Tribune also highlights potential collaboration opportunities between Intel and SK hynix, noting that the two companies could explore initiatives similar to SK hynix’s HBM and advanced packaging partnership with TSMC.

>The report adds that SK hynix is testing the integration of its HBM with Intel’s EMIB-based 2.5D packaging technology, evaluating its potential to combine memory and system semiconductors. As AI demand drives the need for advanced packaging capacity, Green Economy News reports that Samsung and Micron are also assessing EMIB’s compatibility and power efficiency, reflecting memory makers’ broader push toward diversified packaging solutions amid the tight supply of TSMC’s CoWoS.

The potential business partnership between SK and Intel isn't confirmed as it might or might not work out but they're continuing talks to look into this further. Could be good.

Full article - Trendforce (no paywall)

>NVIDIA has reportedly notified its add-in card partners of another GPU kit price increase, this time covering both GDDR7 and GDDR6 memory. This means the raise isn't limited to current Blackwell cards and could affect older GeForce products still using GDDR6 as well.

>The report comes from BenchLife via VideoCardz and follows a similar price adjustment for the RTX 5090 and RTX 5090D V2 back in May. NVIDIA supplies board partners with GPU and VRAM bundled together as a kit, so when memory costs go up, AIBs have little choice but to pass that along to retail pricing. BenchLife notes that partners are also seeing higher costs for coolers, PCBs, and packaging on top of the memory increases, though those secondary cost pressures are described as smaller than the memory-related ones.

>The RTX 50 SUPER series is also affected by this. We've previously reported that those cards are on hold partly due to the cost of 3 GB GDDR7 modules. Inside sources say that each of those GDDR7 modules costs about $60-$70, roughly three times the cost of a 2 GB module at around $20. This adds a significant price premium on SUPER cards since the RTX 5070 SUPER was expected to be upgraded to offer 18 GB, while the RTX 5070 Ti SUPER and RTX 5080 SUPER would each provide 24 GB of GDDR7 memory. GPU prices have already increased 20-30% above where they were not long ago, and this latest round of kit price increases suggests there's more pressure to come. Previous-gen cards that use GDDR6 have been less affected up to now, but that appears to be changing.

Price increases were confirmed for consumer/workstation GDDR7 GPUs from NVIDIA a while back but now it might affect their GDDR6 GPUs too - more signs that the supply and demand for memory isn't stopping but getting constrained further.

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>AMD has introduced the Instinct MI455X, its CDNA 5 data center GPU for large AI training, inference and rack-scale systems. The accelerator includes 432GB of HBM4 memory and offers up to 23.3 TB/s of peak memory bandwidth.

>AMD lists 320 billion transistors and a 2nm process node. The package combines several process technologies rather than using one node for every chiplet.

>Eight compute dies and twelve HBM4 stacks

>The MI455X uses eight Accelerator Complex Dies manufactured on TSMC N2. These chiplets provide 256 active Work Group Processors. AMD also uses two N3P Fabric and Cache Dies and two N3P I/O Dies.

>Twelve HBM4 stacks connect through a 192-channel memory interface. The GPU has 192MB of global L2 cache, split into two 96MB sections. Its I/O configuration supports two PCIe Gen 6 links or three AMD AI-NICs using UALink.

AMD also needs tons of HBM4 for their newly announced datacenter CPUs yesterday so the demand and scaling continues and heats up not just on NVIDIA's front, but for a competitor too as they both need it.

Full article (no paywall)

>AMD has introduced the Instinct MI455X, its CDNA 5 data center GPU for large AI training, inference and rack-scale systems. The accelerator includes 432GB of HBM4 memory and offers up to 23.3 TB/s of peak memory bandwidth.

>AMD lists 320 billion transistors and a 2nm process node. The package combines several process technologies rather than using one node for every chiplet.

>Eight compute dies and twelve HBM4 stacks

>The MI455X uses eight Accelerator Complex Dies manufactured on TSMC N2. These chiplets provide 256 active Work Group Processors. AMD also uses two N3P Fabric and Cache Dies and two N3P I/O Dies.

>Twelve HBM4 stacks connect through a 192-channel memory interface. The GPU has 192MB of global L2 cache, split into two 96MB sections. Its I/O configuration supports two PCIe Gen 6 links or three AMD AI-NICs using UALink.

AMD also needs tons of HBM4 for their newly announced datacenter CPUs yesterday so the demand and scaling continues and heats up not just on NVIDIA's front, but for a competitor too as they both need it.

Full article (no paywall)

SK hynix is reportedly stepping up development of 3D-stacked DRAM, a next-generation memory technology for on-device AI. According to ZDNet, the company has reportedly begun recruiting 3D-Stacked DRAM-on-Logic Design Engineers through its U.S. subsidiary in San Jose, California. SK hynix is also said to have partnered with a specific customer to develop applications for the technology.

This marks the first time SK hynix has recruited specialists dedicated to 3D-stacked DRAM. As the technology gains attention as a next-generation memory solution for on-device AI, the move is seen as an early effort to prepare for commercialization.

3D-Stacked DRAM-on-Logic: A Next-Generation Memory Architecture

In the job posting, SK hynix said it is seeking engineers to work closely with a U.S. customer to co-design logic dies for 3D-Stacked DRAM-on-Logic, an advanced packaging architecture that vertically integrates DRAM directly on top of a system-on-chip. Unlike package-on-package (PoP), which stacks separately packaged chips, 3D-Stacked DRAM-on-Logic enables much shorter interconnects and more data I/O channels within the same footprint. This can reduce data-transfer latency while improving power efficiency and space utilization, as the report highlights.

The technology is being developed primarily for on-device AI. Because these applications require both high memory bandwidth and low power consumption, conventional package-on-package (PoP) architectures have been identified as a performance bottleneck. The report notes that mobile application processors (APs) are viewed as one of the technology’s most promising applications. As the main processors in smartphones, they rely on some of the industry’s most advanced foundry processes and packaging technologies to support on-device AI. Apple and Qualcomm are among the leading designers of mobile APs, the report adds.

Full article (Trendforce - no paywall)