Seeking alignas intuition and resources
Hi, all:
I've been experimenting with alignas after reading this post. Applying it is unintuitive to me, I'm not sure when I'd use this optimization method other than just trying it and measuring. From the article:
> Another important thing to note is that read (readIdx_) and write (writeIdx_) indices are aligned to the size of a cache line (alignas(64)). This is done to reduce cache coherency traffic. On AMD64 / x86_64 and ARM a cache line is 64 bytes, on other CPUs you need to adjust to the appropriate alignment, using std::hardware_destructive_interference_size is a good choice if it’s available. It can also be interesting to try aligning to a multiple of the cache line size in case adjacent cache lines are being pre-fetched.
Is it really as simple as aligning your structs and members on 64 bytes? I'm looking for some more reading on the subject.
Thanks