u/Spiritual-Frame-6791

Hey guys , I’m a recent graduate in EEE and I have been writing RTL using VHDL for like a year now but i still consider myself as a beginner. I write my own RTL code and always try to troubleshoot any problems I may face but sometimes I brainstorm with AI if I can’t solve the problems on my own however I never let AI generate my VHDL code.

There is a sentiment that AI will eventually get into FPGA design ( maybe it has already) but I wanted to ask those who are in the industry how much they use AI in their workflow. Will it ever get to a point where AI will be capable to design and implement complex RTL projects without any supervision?

I genuinely enjoy Digital Design but part of me is really anxious about this since the job market has been tough for entry level positions lately. Please if there is any Senior FPGA Engineers I would really appreciate your insight on this.

I recently finished all my courses with a GPA of 3.84 , however I still had mandatory internships that were pending . During the graduation ceremony I learned that the top student in the whole faculty had a GPA of 3.8 and the top student in my department had a GPA of 3.79. I know GPA isn’t everything but in this context I somewhat expected an honorable mention since I worked hard for 4 years especially since an internship doesn’t affect the GPA. I know i’m not entitled to anything since I technically didn’t graduate but not even a single mention felt unfair from an academic standpoint . I also understand that rules are rules but my friend from another department got recognition despite having a missing internship like me which means the rules were not strictly enforced. Maybe I am wrong but shouldnt academic integrity prevail when challenged with bureaucracy? Perhaps I am wrong and stand to be corrected. If this has ever happened to any of you please share 🙏.

DNN Accelerator Block Diagram

Hi guys, I was finally able to finish my Q4.4 Custom Deep Neural Network Accelerator project I built from scratch using VHDL on Vivado. It consists of a parameterized MAC Array which can have 1 to 64 (2^K) Serial MAC units running computations simultaneously under the control of the MAC Array Control Unit. Other core modules include Input Features Buffer, Parameter Buffer, Activations Buffer, Activations FIFO , ReLU and Argmax Activation blocks. I wont go into details about the core modules but you can check out my last post.

DNN Accelerator Simulation showing the final ARGMAX output which corresponds to digit 3

Simulation showing intra-layer processes(zoomed in)

The goal was to be able to run inference for any classification model with no more than 64 neurons per layer , so for simulation I decided to use a pretrained speech recognition model of network topology (64:32:10) neurons per layer for digits 0-9 .I took the Q4.4 quantized features from the model test set (64 features by the way) and started running predictions in Vivado Simulator and it worked perfectly. I even synthesized and implemented the design and achieved an Fmax of 89MHz (not high) but I decided to still test it out on my Basys3 FPGA and it is failing horribly. I know I still haven't pipelined the design yet but I still expected it to not be that bad. I dont know if maybe the parameters were not loaded correctly into BRAM or something else. This is my first big project so I have a lot to learn and I would really appreciate if anyone could explain to me why this happens.

RTL Schematic

Resource Utilization Report

Implemented Design and Timing Report

Hi guys , I’m currently working on a Q4.4 MAC Array based Neural Network Accelerator on an FPGA for a speech recognition model which identifies digits 0-9. I am designing the whole architecture from scratch . Audio input capture and data preprocessing will be handled by my PC and input features data will be sent to the FPGA via USB-UART at 9600baud. I am almost done but I’m not sure if it’s a really good project to add on my Resume. I understand that the competition in the FPGA design industry is insane right now even just for internship roles and I want to work on projects that actually matter.

So far I have designed and simulated all the core modules which include Parameter Buffer, MAC Array(Serial MAC units) , MAC Array Control Unit ,Input Features Buffer(UART RX + Async FIFO + Clock Divider), Activation Buffer, Parameters BRAM, Activations BRAM ,ReLU and Argmax Activation modules. You can check out the simulations below :

MAC Array(4 Serial MAC units) :Handles dot product computations

https://preview.redd.it/emxw3dxa684h1.png?width=1365&format=png&auto=webp&s=db0b655c74f18bd94f14b1ca28eac03eb1f3c31c

MAC Array Control Unit: Controls data movement(input features, parameters ,activations) and computation processes

https://preview.redd.it/6nsybzbp684h1.png?width=1363&format=png&auto=webp&s=7e992fb0977ea0bca01772d65487284a5e8a5043

MAC Array Control Unit State Diagram

https://preview.redd.it/oav4u7tx684h1.jpg?width=1600&format=pjpg&auto=webp&s=76d43e6bb344584479a6089b2391c6afa6f210e6

Input Features Buffer: Receives data from PC and stores it in FIFO temporarily.

https://preview.redd.it/w86u1qe7784h1.png?width=1357&format=png&auto=webp&s=5588eb6357e225dba9e41215a4bb9416e9cdbea4

Parameter Buffer: Fetches parameters from Parameters BRAM and feeds them to their designated MAC unit for computation

https://preview.redd.it/6ed8ou3h984h1.png?width=1220&format=png&auto=webp&s=fafe359d616ee2bcc5991e8dcb814d647977e793

Activation Buffer: Temporarily stores activations and feeds them into Activations BRAM

https://preview.redd.it/xvk2h5bkb84h1.png?width=1365&format=png&auto=webp&s=765a27364def2d7cffeced48a510f44599ccded6

Argmax Activation : determines the highest activation in the output layer

https://preview.redd.it/73u1vpwhd84h1.png?width=1365&format=png&auto=webp&s=b0db38d77ebca3a45795e1f4bf3a187fbace3b1b

Hi guys , for anyone in Türkiye who landed a summer internship this year or last year. How did you do it because i’ve been getting rejection letters only . Which projects landed you an interview? , maybe I am working on the wrong projects . Please help.