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u/ThatOrganicArtist

r/FPGA r/Verilog
Finished implementing UART, SPI and I²C from scratch in Verilog
▲ 77 r/FPGA

Finished implementing UART, SPI and I²C from scratch in Verilog

Over the past month, I've been learning serial communication protocols by implementing them in Verilog.

I started with UART, then moved to SPI, and finally finished I²C. I've now put all three into a single repository.

Some of the main features:

  • UART: TX/RX, 16× oversampling, parity and error detection
  • SPI: Master/Slave, all four CPOL/CPHA modes, full-duplex communication
  • I²C: Master/Slave, 7-bit addressing, ACK/NACK, READ/WRITE and multi-byte transfers
  • Parameterized RTL and self-checking verification across the designs.

One thing I found interesting was how different the implementation difficulty was despite all three being serial protocols. UART was relatively straightforward once the sampling logic was sorted out, SPI introduced clock-edge/phase handling, while I²C was easily the most annoying one to debug because both devices share the same bus and SDA has to be released/driven at exactly the right points.

I'd really appreciate feedback on the implementations, verification approach, or anything you'd change to make these closer to practical, reusable communication IP.

(I know many will suggest it is high time to start using SystemVerilog... I promise it's the next thing i am learning lmao)

GitHub: https://github.com/theYash856/Communication_Protocols

Could've posted this earlier, but GitHub decided to go down precisely when I was about to upload the project 😭

u/ThatOrganicArtist — 3 days ago
▲ 41 r/FPGA

Designed and Verified a UART Transceiver in Verilog

After finishing my 4-bit Multi-Cycle CPU, I started learning communication protocols and began with a UART Transceiver.

The last project I shared here was my 4-bit Multi-Cycle CPU. A lot of the feedback I got was about improving my verification methodology and documentation. I tried to apply those suggestions in this project.

Some of the new things I focused on were:

  • Reusable testbenches using tasks to automate repetitive test sequences.
  • Self-checking pass/fail tests with a summary printed to the console.
  • Better documentation, included a table of all test cases performed and detailed explanations of the bugs and how they were fixed.

Would love any feedback on both the design and the verification approach.

Repo: https://github.com/theYash856/UART-Transceiver

u/ThatOrganicArtist — 1 month ago
▲ 57 r/FPGA

I built a 4-bit CPU as a personal project and wanted technical feedback.

I recently designed and documented a 4-bit multi-cycle CPU in Verilog HDL as a personal learning project after completing my college's Digital System Design course.

Although the project has only been simulated so far, my goal is to eventually implement similar designs on an FPGA as I continue learning. Along with the RTL, I documented the ISA, CPU architecture, module design, execution flow, debugging experience, and design decisions to treat it more like a technical project than just a coding exercise.

I'd really appreciate feedback on what to improve before taking a design like this to actual hardware.

Repository:

https://github.com/theYash856/4\_bit\_Multi\_Cycle\_CPU

Any constructive criticism is more than welcome.

reddit.com
u/ThatOrganicArtist — 2 months ago
▲ 4 r/Verilog

I built a 4-bit CPU as a personal project and wanted technical feedback.

I recently designed and documented a 4-bit multi-cycle CPU in Verilog HDL as a personal learning project. This comes after I completed the standard Digital System Design (DSD) course of my college.

I tried to document in a technical report format, explaining the ISA, specs, architecture, design decisions and debugging experience.

I would really appreciate technical feedback from people with more experience, any issue with the structure, design or anything else that could help me improve future projects.

GitHub repo: https://github.com/theYash856/4\_bit\_Multi\_Cycle\_CPU

Any constructive criticism is more than welcome.

reddit.com
u/ThatOrganicArtist — 2 months ago