u/amykyta3

Hello!
As many of you may know, I'm the main author and maintainer of the open-source PeakRDL and SystemRDL compiler projects. For those unfamiliar, these are tools that help automate the boring and tedious parts of RTL design - control & status register automation.

I recently checked and between these projects, we've reached over 10M downloads! As a thanks to everyone that has contributed to the projects, told their friends about PeakRDL, or simply used the tools at work or at home, I wanted to share some free stickers I made.

If you want some stickers, DM me with mailing info and a quick note about how you've used PeakRDL or SystemRDL.

Hey r/FPGA!

I'm excited to share a silly little extension to PeakRDL I made, and just did a talk on this past weekend at FOSSi's Latch-Up conference. PeakRDL-PyRAL generates Python Register Abstraction Layers (RALs), something I hope the community finds useful!

If you've used something like this already (like PeakRDL-python, cocotb-ralgen, or similar), this will likely look very familiar. My main motivation for implementing PeakRDL-PyRAL was to make something that scales better for enormous designs (like SoCs with millions of registers in their address spaces). PeakRDL-PyRAL's load time and memory usage is design-size invariant (O(1)) which is a big deal when instrumenting large systems.

Check out the docs here for much more details on what it can do: https://peakrdl-pyral.readthedocs.io