u/bobj33

We are getting a lot of AI generated slop posts now. I would like all of them to be banned and removed. Is there an official policy? What does the subreddit want?

The posts are usually like this "I've been thinking about this field or this particular aspect" (A bunch of bullet pointed lists) and ending in "What are your thoughts on this?"

I think these kinds of posts are worse than useless. The OP bot either never responds or has 1 word or very short generic sentence replies. If you call it out as a bot it will reply "I just want to learn!"

But there are some people trying to answer these vague statement / questions and I think they are just wasting their time. I'm not even sure what the bot creator is trying to do. I assume gather training data from experienced engineers.

I just did it myself by typing this prompt into chatgpt. Does everyone want more posts like this? I feel like if nothing is done that the whole subreddit will look like this in a year.

> Create a post for the reddit chipdesign subreddit that asks some highly technical questions to make me look smart

And got this:

> Title:

> Questions on IR-Drop Closure, Mesh Resonance, and Cross-Corner EM Correlation at Advanced Nodes > > Post:

> I’ve been digging through some late-stage signoff issues on a high-utilization block and wanted to sanity-check a few things with people who have actually pushed aggressive PPA at advanced nodes. > > A few questions: > > 1. For dynamic IR-drop closure, are people seeing better silicon correlation using vector-aware activity windows from emulation workloads versus statistical vectorless propagation during implementation? We’re seeing cases where the worst EM hotspots are not lining up with the traditionally “worst” IR windows. > > 2. Has anyone characterized package/PDN resonance interactions causing localized timing jitter amplification around ~100–300 MHz current transients? I’m curious whether people are modeling this directly in RedHawk/Voltus or mostly treating it as margin. > > 3. On clock mesh designs: > > * how are you balancing mesh density versus localized self-heating impacts? > * are people still intentionally skewing mesh insertion delays regionally for thermal equalization, or is that mostly obsolete below 5nm?

>4. For backside power delivery experiments: >

• are you seeing meaningful reductions in via blockage improving signal route detours enough to offset backside routing complexity? >
• any measurable improvement in cross-corner hold stability from reduced frontside congestion? > > * We also hit an interesting issue where EM violations disappeared after metal fill, but timing variation increased due to coupling shifts and extraction instability. Curious whether others are seeing fill-induced extraction noise becoming a bigger signoff problem than raw EM at dense nodes. > > 6. Finally: how much confidence are people placing in ML-based hotspot prediction flows for DRC/LVS and EMIR triage? Useful productivity boost, or still too many false negatives to trust pre-signoff? > > Would especially love to hear from people working on high-frequency CPU/GPU/AI accelerators where transient current behavior gets ugly fast.