u/der_vur

Hello everybody, I used to use Stirling Bank as Euro account but with Monzo opening it I did a wee comparison and thought I would share it with you.

On the paper Monzo is supposed to be better, as it gives 0.25% markup on the exchange rate, while Stirling bank is supposed to have the correct exchange rate but a fee of 0.4%. But I decided to try transferring 10€ as a test anyway and to share it with you. You can see the screenshot (with the last one being the result of asking the conversion on iOS). Both transfers were done within a minute to each other.

Not only the conversion is better but also other features. Monzo partnered with a European company, so your IBAN is a Netherland one (as opposed to Stirling's UK IBAN). This gives you access to SEPA instant transfers (not supported by Stirling), and confirmation of the sender (not supported by Stirling).

The latter can seem sketchy because when sending money from Europe to Stirling account the EU bank issues a warning saying that they couldn't verify the account name.

I think also Revolut allows exchanges but I don't have an account with them so I can't compare.

As a long time Batman fan I actively avoided purchasing anything Batman related 😅

Hello there, as the question states I have a design that works perfectly fine when it is just a Vivado project but once I package it into an IP and use it in a block diagram... it stops working.

I'm using a ZCU104 and an ADC FMC board Alinx FL9613. To say it shortly, when using the normal RTL project, the clock on the AD9518 on the aforementioned ADC board locks fine (the ADC chips are in reset state until the clock locks). But once I package it into an IP and use it in a block design it does not work anymore.
At first I thought the problem was PYNQ because it wasn't working with PYNQ (I made a post about it and I go into more details in the PYNQ forum: https://discuss.pynq.io/t/external-adc-does-not-work-in-pynq-but-it-works-if-loading-the-bitstream-in-vivado/9114).

But yesterday I decided to make a step back and package the code in an IP without any AXI interfaces and have a block design with only my IP, a clock wizard and an ILA... the clock chip still does not lock...

I'll be back in the office on Monday and try importing the RTL in the block design directly instead of the IP, but if that doesn't work I'll be at a loss cause I truly do not know what else to try. If anybody has an idea of why a design would work fine on its own but not as an IP or a block diagram or has ideas on other debugging steps please let me know! I double checked the code and constraints plenty of times in the past two weeks and can't find anything out of the ordinary.

In the block design I let Vivado generate the port (right click on IP generate external ports). Could that be an issue? I double checked the wrapper and the ports are correctly set to in, out or inout.

In the PYNQ forum post you can download the code. It is mainly the one provided by Alinx with only a few tweaks here and there.

Edit: While I'll be in the office on Monday, I have the laptop with me at home over the weekend so if you require extra screenshots or the actual projects, or anything else please let me know as I can provide those over the weekend!