FABulous 2.0 released: open-source, silicon-proven eFPGA generator (fabric definition to GDSII)
FABulous is an open-source embedded FPGA (eFPGA) generator. You describe a fabric in a few files, and it produces the RTL, an open CAD flow built on Yosys and nextpnr for compiling user designs onto the fabric, and a tapeout-ready GDSII. It is silicon-proven, with 12+ tapeouts across five process nodes (TSMC 180nm, SkyWater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS), and supports frame-based partial reconfiguration of individual fabric regions at runtime.
v2.0 is effectively a rewrite since the 1.3 stable version. Main changes:
- Full LibreLane GDS flow: generate a tiled, optimised GDSII straight from a fabric definition.
- Automatic tile generation from your own primitives, rather than writing tiles by hand.
- Run it in the browser: GitHub Codespaces ships the whole toolchain plus the FABulator GUI, zero install, so you can browse/edit a fabric and compile a tile from a browser tab. A Dev Container gives you the same environment locally.
- Repackaged as a proper Python package (pip install fabulous-fpga), with a new typer/cmd2 CLI + REPL and a uv-based dev workflow (Python 3.12).
- Plus named fabrics, a Nix dev environment (FABulous nix-env) and Docker image, SystemVerilog/.sv handling, blackbox BELs, out-of-tree BEL paths, and a big docs overhaul.
Repo: https://github.com/FPGA-Research/FABulous
Docs and chip gallery: https://fabulous.readthedocs.io/
Release notes: https://github.com/FPGA-Research/FABulous/releases/tag/v2.0.0
Quick start:
pip install fabulous-fpga
FABulous create-project demo
cd demo && FABulous start
Feedback welcome, especially on the GDS flow and anything that breaks.