r/ASIC

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FABulous is an open-source embedded FPGA (eFPGA) generator. You describe a fabric in a few files, and it produces the RTL, an open CAD flow built on Yosys and nextpnr for compiling user designs onto the fabric, and a tapeout-ready GDSII. It is silicon-proven, with 12+ tapeouts across five process nodes (TSMC 180nm, SkyWater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS), and supports frame-based partial reconfiguration of individual fabric regions at runtime.

v2.0 is effectively a rewrite since the 1.3 stable version. Main changes:

• Full LibreLane GDS flow: generate a tiled, optimised GDSII straight from a fabric definition.
• Automatic tile generation from your own primitives, rather than writing tiles by hand.
• Run it in the browser: GitHub Codespaces ships the whole toolchain plus the FABulator GUI, zero install, so you can browse/edit a fabric and compile a tile from a browser tab. A Dev Container gives you the same environment locally.
• Repackaged as a proper Python package (pip install fabulous-fpga), with a new typer/cmd2 CLI + REPL and a uv-based dev workflow (Python 3.12).
• Plus named fabrics, a Nix dev environment (FABulous nix-env) and Docker image, SystemVerilog/.sv handling, blackbox BELs, out-of-tree BEL paths, and a big docs overhaul.

Repo: https://github.com/FPGA-Research/FABulous
Docs and chip gallery: https://fabulous.readthedocs.io/
Release notes: https://github.com/FPGA-Research/FABulous/releases/tag/v2.0.0

Quick start:

pip install fabulous-fpga

FABulous create-project demo

cd demo && FABulous start  

Feedback welcome, especially on the GDS flow and anything that breaks.

A lot of students want to enter semiconductor design, but many get confused about where to start.

Some jump directly into physical design.
Some start with RTL.
Some try analog first.
Some only watch videos and collect certificates.

In my opinion, a beginner-friendly roadmap should look something like this:

1. CMOS Understand transistors, basic circuits, SPICE simulation, and how devices behave.
2. RTL Learn Verilog, digital logic design, testbenches, and simulation.
3. Physical Design Understand synthesis, floorplanning, placement, CTS, routing, timing, and how RTL becomes layout.
4. Physical Verification Learn DRC, LVS, antenna checks, density, PEX, and what it means to make a design tapeout-ready.

For someone who already knows RTL and basic physical design, jumping directly into an internship-style physical design project may make more sense than restarting from zero.

The bigger point is this:

Interest in semiconductors is not enough anymore. Students need proof — GitHub work, simulation results, reports, screenshots, debug notes, and projects they can explain.

Curious to hear from people already working in VLSI / semiconductors:

Would you change this order?
Should beginners start with CMOS first, or RTL first?
What would you tell a student who wants to enter chip design seriously in 2026?

Looking for Off-Campus Intern/Entry Level Roles (INDIA)

Target Roles: Design and Verification, Computer Architecture (I have a very limited exposure to Physical Design)

Gave many off-campus interviews last semester, but couldn't clear a few, and some just didn't work out at the end

Now doing a Research Internship in an IIT, related to FPGA and ASIC design optmisations of PRNGs for BIST

I have attached my Resume in the post, please take a look

Any tips, suggestions or referrals will help a lot!

Hello can I please get a rate of my resume. I'm going into my last year of undergrad and im looking to go to grad school (prob PHD). I have a deep passion for optimization and want to get into FPGA/ASIC design. I didn't include my gpa because it is low IMO but it is a 3.30/4.00. I really didn't find my passion untill 2 years ago and slacked off in the begining.

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