r/ASIC

Free cloud-based VLSI labs that run in one click. No install. No excuse. Do something with your summer.
▲ 271 r/ASIC+4 crossposts

Free cloud-based VLSI labs that run in one click. No install. No excuse. Do something with your summer.

Every summer I watch people in this field complain about not getting placed, not having experience, not knowing where to start.

So here. Free. Cloud. One click. No setup. No install. No excuse.

VSD has put together free GitHub-based programs for every major area of VLSI and semiconductors. Each one has a cloud lab you open in a browser and start immediately. Build the repo. Show the work. That is what gets you hired.

Physical Design (SoC Design and Planning)

Free: https://github.com/fayizferosh/soc-design-and-planning-nasscom-vsd

Cloud lab: https://github.com/vsdip/vsd-openlane

RISC-V Based MYTH

Free: https://github.com/AnoushkaTripathi/NASSCOM-RISC-V-based-MYTH-program

Cloud lab: https://github.com/vsdip/vsd-riscv2

Semiconductor Packaging

Free: https://github.com/arunkpv/Semiconductor-Packaging

Lab (Windows): https://www.ansys.com/en-in/academic/students/ansys-electronics-desktop-student

CMOS Circuit Design — start here if you are new to this

Free: https://github.com/PRIYANKADEVYADAV15/CMOS-Circuit-Design-Spice-Simulation-using-Sky130nm-technology

Cloud lab: https://github.com/vsdip/vsd-cmos/

RTL Design and Synthesis — also a great starting point

Free: https://github.com/vlsienthusiast00x/RTL_workshop

Cloud lab: https://github.com/vsdip/vsd-rtl

TCL Programming — do this one regardless of where you are in your career

Free: https://github.com/AnoushkaTripathi/VSD_TCL_PROGRAMMING_WORKSHOP/

Cloud lab: https://github.com/vsdip/vsd-tcl

7nm FinFET Design

Free: https://github.com/arunkpv/vsd_asap7_workshop

Cloud lab: https://github.com/vsdip/vsd-7nm

FPGA Fabric Design and Architecture

Free: https://github.com/ShonTaware/FPGA_Design_Fabric_Architecture

Cloud lab: shared during workshop

RISC-V Edge AI

Free: https://github.com/AayusHJainCodely/Risv_Edge_AI

Cloud lab: https://github.com/vsdip/vsd-riscv-edgeai

Analog Bandgap IP Design

Free: https://github.com/chandranshu24-hue/bgr_chandranshu/blob/main/README.md

Cloud lab: https://github.com/vsdip/vsd-bandgap/

All of this is free. All labs run on the cloud. You do not need a beefy machine, you do not need to configure a Linux environment, you do not need to buy anything.

What you do need is to stop waiting and start committing to GitHub.

The semiconductor industry does not care about what you watched on YouTube this summer. It cares about what you built.

u/kunalg123 — 2 days ago
▲ 58 r/ASIC+2 crossposts

Are you programming a chip or designing hardware? A simple FPGA vs development board interview question

Many beginners treat development boards and FPGA boards as similar because both can blink LEDs, read sensors, drive motors, or connect to peripherals.

But internally, they represent two very different learning paths.

On a development board, the chip architecture is already fixed. You write C, Python, or Arduino-style code, and an existing processor executes those instructions.

On an FPGA board, you are not just writing software. You are describing hardware using Verilog or VHDL. The FPGA fabric gets configured into actual digital logic such as counters, UARTs, PWM blocks, small CPUs, accelerators, or custom datapaths.

That is the key difference:

Development board = software running on fixed hardware.

FPGA board = custom hardware built inside programmable silicon.

This is a simple question, but I think it quickly reveals whether someone understands the difference between embedded programming and digital hardware design.

For students entering RTL design, FPGA design, SoC design, or hardware acceleration, this clarity is important.

Blinking an LED is easy. Understanding whether the blink came from a software instruction or synthesized hardware logic is where real hardware learning begins.

Curious to hear from others: how would you explain this difference to a beginner in one line?

u/kunalg123 — 5 days ago
▲ 148 r/ASIC+4 crossposts

Most Students Use FPGA Like a Black Box. Here’s How to Actually Understand the Fabric Inside.

Most students use an FPGA like a black box.

They write Verilog, press synthesize, generate a bitstream, and celebrate when the LED blinks.

That is a good starting point, but the real learning begins when you understand what is actually inside the FPGA fabric.

A LUT is not just a “logic block”. It is a tiny programmable memory that can implement any Boolean function for a given number of inputs. Once you connect LUTs with flip-flops, multiplexers, connection boxes, switch boxes, and programmable routing, an FPGA stops looking like magic. It starts looking like architecture.

This is the difference between someone who only knows how to use FPGA tools and someone who understands how FPGA hardware is built.

For students aiming at FPGA prototyping, ASIC front-end design, verification, embedded systems, AI/ML acceleration, or hardware architecture roles, this foundation is extremely useful.

Basic Verilog is important, but stopping at Verilog is not enough. Understanding LUTs, CLBs, slices, routing, interconnects, waveform debugging, testbenches, and simple FPGA fabric modeling gives much deeper confidence.

We are running a 10-day cloud-based FPGA Fabric Design and Architecture Workshop at VSD, where the focus is on understanding FPGA internals from the ground up. No FPGA board is mandatory, and the labs are simulation-ready using Vivado and GTKWave.

If you are serious about FPGA, don’t stop at blinking LEDs.

Learn the fabric.

Registration link in comments.

u/kunalg123 — 8 days ago
▲ 2 r/ASIC+2 crossposts

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u/Salty_Perspective_34 — 7 days ago
▲ 1 r/ASIC

RTL for asic as opposed to fpga deployment.

Hello everyone, I recently completed a BNN accelerator for a ultrascale. During this project I fell in love with timing and resource optimization and PPA analysis/tradeoff. During this project I capped out the frequency of the ultra scale and got my critial path to result in fmax of 945Mhz.

Because of this I realized that I want to write RTL for asics/chips as opposed to fpga's. Does the optimization carry over to asics? Also how would I transition to rtl for asics, is there any project I should do?

reddit.com
u/vbonecrusher1014 — 8 days ago
▲ 2 r/ASIC+1 crossposts

Do I need a masters to get into ASIC

Hey I’m about to finish my last year of ECE. I’ve done a 16month internship in controls design and frankly I don’t like it. Im really interested in hardware engineering specifically ASIC engineering and chip design. I heard that you need a masters to get into asic engineerin. In Ontario we have a MASC (research based and 2 years)and a MEng(course/project based 1 year). What should I do if I want to get into ASIC and What Masters program should I do if I need one. Do I need one? is there a road map I should follow?

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u/BAISAAB — 9 days ago
▲ 17 r/ASIC+3 crossposts

ASIC Senior Engineer salary for PhD+1 year postdoc with no industry experience

I am being considered for a Senior ASIC / RTL Design Engineer role in Qualcomm India. My background is: PhD, MTech and BTech in EE/ECE from an IIT Around 1 year of postdoctoral research experience Research experience in DSP/VLSI, algorithm-to-architecture mapping, RTL design, ASIC/FPGA-oriented implementation, low-power/high-speed design concepts Publications/patents in signal processing/VLSI-related areas Academic/postdoc experience, but no long full-time industry experience yet The role is broadly related to wireless/DSP IP design, microarchitecture, RTL coding, front-end ASIC design, synthesis/STA awareness, lint/CDC, and low-power/high-speed design. I wanted to understand the current realistic compensation range in India for someone with this profile. Specifically: What CTC range should I expect for a Senior ASIC Design Engineer / Senior Engineer-level role at Qualcomm India? How is the CTC usually split between base salary, bonus, RSUs, joining bonus, and other benefits? Does a PhD + postdoc usually help in negotiation, or is it mostly treated similar to a fresh PhD entry? Is there a meaningful difference between Senior Engineer, Staff Engineer, and Senior Staff Engineer levels for PhD candidates in Qualcomm India? What range would be reasonable to negotiate for in 2025–2026 market conditions?

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u/Good_Layer_4623 — 14 days ago