r/ASIC

I'm running a CV32E40P-based SoC through the open-source ASIC flow using LibreLane 3.0.6, sky130A, and sky130_fd_sc_hd, and I'm trying to sanity-check the Fmax I'm getting.

After post-route STA with extracted parasitics (RCX), my worst setup path is entirely inside the CV32E40P multiplier:

startpoint : ex_stage_i.mult_i.mulh_CS[0]
endpoint   : ex_stage_i.mult_i.int_op_a_msu[19]
logic depth: 82 stages
data path  : 26.9 ns
             19.5 ns cells
              7.4 ns repeaters / long nets

With a 22 ns clock target, I get roughly:

ff_n40C_1v95    +12.8 ns slack  -> ~110 MHz Fmax
tt_025C_1v80     +7.4 ns slack  ->  ~68 MHz Fmax
ss_100C_1v60     -5.7 ns slack  ->  ~36 MHz Fmax

So at the slow corner I'm effectively limited to around 36 MHz, while TT is closer to 68 MHz.

A few things I'm wondering about:

1. Does ~36 MHz at ss_100C_1v60 sound reasonable for CV32E40P on SKY130/HD? I'm mostly trying to figure out whether this is in the expected ballpark or whether something in my flow/physical design is clearly suboptimal.
2. Has anyone pipelined or otherwise modified the CV32E40P multiplier for timing? The critical MULH path goes through the multiplier state machine (STEP0 -> STEP1 -> STEP2). Since the state advances every cycle, I don't think simply declaring it multicycle would be functionally correct.
3. How would you approach the physical side? Around 28% of the critical-path delay is from buffers/repeaters on long nets. The full SoC is fairly large (~13 mm²) because it also contains an accelerator and several SRAM macros. Would you normally:
   • constrain the CPU into a tighter placement region,
   • improve macro placement / floorplanning,
   • use a different standard-cell library,
   • or tackle the multiplier architecture itself first?

I'm not looking for a magic OpenROAD setting — mainly interested in real-world SKY130 numbers from people who have implemented CV32E40P or similar RISC-V cores.

Is ~35–40 MHz slow-corner signoff basically expected here, or does this look like I'm leaving a lot of performance on the table?

I am learning PD and currently I am working with Skywater 130nm, but the issue is it only has 5 layers, in which I usually reserve last 2 layers for PDN and CT, so I often encounter congestion issues ...