Built a hardware scan-line triangle rasterizer from scratch, full writeup here if interested
https://mummanajagadeesh.github.io/blogs/rasterizer/
It’s simulation-based for now, asking for feedback/suggestions on improvements
Curly, dry, frizzy. Been using only shampoo my entire life and nothing else. Zero conditioner, zero mask, zero anything.
Just started looking into curl care and I'm lost. Open to both combo kits and individual product recommendations, available in India. Price is not a concern.
(attaching photos so you can see the damage yourself)
Built RV32IM variants across single-cycle, pipelined, superpipelined, superscalar and OoO on actual simulation with CoreMark + custom micro-kernels covering low-high ILP, ALU-heavy to mem-heavy and ctrl-stressed patterns
Pipelined gains in order:
CPI 1.31→1.06, CoreMark/MHz 2.57→3.17, within 2.3% of an unoptimised dual-issue superscalar
Same load-forwarding fix that gave +2% on the pipeline gave +17% on the superscalar; a load-RAW stall in dual-issue removes 2 slots per cycle, hazard handling becomes a cross-cycle dual-slot matrix problem
Once both were optimised the 2.3% gap became 46.8%
For more details: link
Toolchain: Verilator, Surfer, Ripes, GCC/LLVM, Spike/QEMU, RISCOF
Built RV32IM variants across single-cycle, pipelined, superpipelined, superscalar and OoO on actual simulation with CoreMark + custom micro-kernels covering low-high ILP, ALU-heavy to mem-heavy and ctrl-stressed patterns
Pipelined gains in order:
CPI 1.31→1.06, CoreMark/MHz 2.57→3.17, within 2.3% of an unoptimised dual-issue superscalar
Same load-forwarding fix that gave +2% on the pipeline gave +17% on the superscalar; a load-RAW stall in dual-issue removes 2 slots per cycle, hazard handling becomes a cross-cycle dual-slot matrix problem
Once both were optimised the 2.3% gap became 46.8%
For more details: link
Toolchain: Verilator, Surfer, Ripes, GCC/LLVM, Spike/QEMU, RISCOF