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u/Large-Raisin-5912

r/chipdesign r/indianhaircareaddicts r/ASIC r/GraphicsProgramming r/vlsi r/ECE r/computerarchitecture r/FPGA
Resume Review | Graduating 2027 | Looking for Off-Campus Intern/Entry Level Roles (INDIA)
▲ 29 r/ASIC+3 crossposts

Resume Review | Graduating 2027 | Looking for Off-Campus Intern/Entry Level Roles (INDIA)

Looking for Off-Campus Intern/Entry Level Roles (INDIA)

Target Roles: Design and Verification, Computer Architecture (I have a very limited exposure to Physical Design)

Gave many off-campus interviews last semester, but couldn't clear a few, and some just didn't work out at the end

Now doing a Research Internship in an IIT, related to FPGA and ASIC design optmisations of PRNGs for BIST

I have attached my Resume in the post, please take a look

Any tips, suggestions or referrals will help a lot!

u/Large-Raisin-5912 — 8 days ago
▲ 15 r/vlsi+1 crossposts

got TI analog intern, have some questions about navigating it

so my friend got an intern at TI (Texas Instruments) through oncampus, analog track, 2 months, india. posting on his behalf

its been a week in and the manager assigned to him is at a pretty senior position and is barely around. no actual work allotted yet, just told to go through some resources and solve the daily problems he gives. this is also apparently the first time this manager is taking interns, and seniors already working there are saying PPO/conversion chances are genuinely tough with him

the bigger issue is our college rules say if he doesnt convert, he cant sit for TI placements again under the analog track. so yeah, stakes are there

hes also the only intern under this manager, no one else to compare notes with or figure out whats normal here

hes doing what hes told for now, solving the problems, going through the resources. but the thing is theres no real project or deliverable yet, so theres nothing to actually prove himself on. hard to make an impression when theres nothing to show

actual questions:

  1. how do you handle a situation where your only shot at proving yourself is daily problems the manager assigns, and thats it? no project, no team interaction, nothing. what does good work even look like here beyond just solving what youre given
  2. hes the only intern under this guy so theres no benchmark either. should he be doing something extra on his own or just wait it out till actual work comes
  3. analog is the priority but analog companies through our college are scarce. hes got decent digital coursework too. should he use whatever free time he has to keep that sharp as a backup, or does splitting focus make things worse

any advice from people who've been through something similar or know how TI internships usually work would actually help

reddit.com
u/Large-Raisin-5912 — 1 month ago
▲ 1 r/indianhaircareaddicts

20M Haircare query, never used conditioner in my life. Hair is dry and frizzy af

Curly, dry, frizzy. Been using only shampoo my entire life and nothing else. Zero conditioner, zero mask, zero anything.

Just started looking into curl care and I'm lost. Open to both combo kits and individual product recommendations, available in India. Price is not a concern.

(attaching photos so you can see the damage yourself)

u/Large-Raisin-5912 — 2 months ago
▲ 35 r/computerarchitecture

Built RV32IM variants across single-cycle, pipelined, superpipelined, superscalar and OoO on actual simulation with CoreMark + custom micro-kernels covering low-high ILP, ALU-heavy to mem-heavy and ctrl-stressed patterns

Pipelined gains in order:

  • Early branch resolution EX→ID: +8.6%
  • 2-bit saturating predictor: +6.5%
  • BTB: +3.5%
  • Generalised MEM-to-EX load forwarding: +2%

CPI 1.31→1.06, CoreMark/MHz 2.57→3.17, within 2.3% of an unoptimised dual-issue superscalar

Same load-forwarding fix that gave +2% on the pipeline gave +17% on the superscalar; a load-RAW stall in dual-issue removes 2 slots per cycle, hazard handling becomes a cross-cycle dual-slot matrix problem

Once both were optimised the 2.3% gap became 46.8%

For more details: link

Toolchain: Verilator, Surfer, Ripes, GCC/LLVM, Spike/QEMU, RISCOF

u/Large-Raisin-5912 — 3 months ago
▲ 2 r/ASIC

Built RV32IM variants across single-cycle, pipelined, superpipelined, superscalar and OoO on actual simulation with CoreMark + custom micro-kernels covering low-high ILP, ALU-heavy to mem-heavy and ctrl-stressed patterns

Pipelined gains in order:

  • Early branch resolution EX→ID: +8.6%
  • 2-bit saturating predictor: +6.5%
  • BTB: +3.5%
  • Generalised MEM-to-EX load forwarding: +2%

CPI 1.31→1.06, CoreMark/MHz 2.57→3.17, within 2.3% of an unoptimised dual-issue superscalar

Same load-forwarding fix that gave +2% on the pipeline gave +17% on the superscalar; a load-RAW stall in dual-issue removes 2 slots per cycle, hazard handling becomes a cross-cycle dual-slot matrix problem

Once both were optimised the 2.3% gap became 46.8%

For more details: link

Toolchain: Verilator, Surfer, Ripes, GCC/LLVM, Spike/QEMU, RISCOF

u/Large-Raisin-5912 — 3 months ago