u/vbonecrusher1014

Hello everyone, I recently completed a BNN accelerator for a ultrascale. During this project I fell in love with timing and resource optimization and PPA analysis/tradeoff. During this project I capped out the frequency of the ultra scale and got my critial path to result in fmax of 945Mhz.

Because of this I realized that I want to write RTL for asics/chips as opposed to fpga's. Does the optimization carry over to asics? Also how would I transition to rtl for asics, is there any project I should do?

Hello everyone, I recently completed a BNN accelerator for a ultrascale. During this project I fell in love with timing and resource optimization and PPA analysis/tradeoff. During this project I capped out the frequency of the ultra scale and got my critial path to result in fmax of 945Mhz.

Because of this I realized that I want to write RTL for asics/chips as opposed to fpga's. Does the optimization carry over to asics? Also how would I transition to rtl for asics, is there any project I should do?

Hello everyone, I recently completed a BNN accelerator for a ultrascale. During this project I fell in love with timing and resource optimization and PPA analysis/tradeoff. During this project I capped out the frequency of the ultra scale and got my critial path to result in fmax of 945Mhz.

Because of this I realized that I want to write RTL for asics/chips as opposed to fpga's. Does the optimization carry over to asics? Also how would I transition to rtl for asics, is there any project I should do?

does anyone know if UF will allow this.