Started investing a couple months ago, I’ve been trying to learn as much about it as possible. Most of my money is in a vanguard ETF and RYCEY, but EnSilica caught my eye and after doing some research I decided it seemed as good a company as any to invest in. I mainly liked how cheap it was, plus its potential, plus the fact it’s not considered a ‘meme stock’.

I’ve got 965 shares at £1.07, it’s been below that for a while, I’m aware I got in late but I’m not too concerned about the constant red I’m in. My main questions are, is this sort of behaviour normal for a company that seems to look really promising? Is the decline from the £1.26 to £0.87 just a price correction? And why does it seem to consistently increase in the morning then decline into the afternoon? Is it a good sign that WSB hasn’t got their sights set on it yet?

I have no interest in selling and cutting my losses, I’m in this for the long term and I’m happy to hold it through red and green, I’m just quite curious to hear from those with more experience!

France’s ANSSI is linking security certification to Post-Quantum Cryptography (PQC) and intends to stop certifying security products that lack quantum-resistant encryption, a move that will ​force government bodies and critical operators to shift away from older ‌systems. ANSSI approval will also be required for use in French government agencies ​and critical infrastructure, making the policy a de facto phase-out of ⁠older encryption.

Samih Souissi, ANSSI's chief of staff, said at the France Quantum conference that the agency would halt such certifications from 2027, and that businesses should be buying only quantum-safe products ​by 2030.

That’s positive news for EnSilica as one of Europe’s leading ASIC semiconductor designers, and one of few firms with expertise and intellectual property for post-quantum cryptography silicon. With their novel 3-in-1 PQC silicon intellectual property and a secure processor for critical infrastructure in development thanks to British government funding, the future bodes well for them in my opinion.

https://www.ensilica.com/news-and-insight/ensilica-cuts-post-quantum-cryptography-pqc-silicon-area-with-three-in-one-ip-block/

https://www.ensilica.com/news-and-insight/quantum-cryptography-processor-chip/

A place for general discussion and events not considered as requiring a dedicated post. Quality contributions of note and depth may eventually go on to form the basis of future curated posts.

Electronically steered antennas are now a core building block for satellite user terminals, especially in low Earth orbit (LEO) constellations and 5G Non‑Terrestrial Network (NTN) deployments. If you are developing user equipment for satellite communications, terminals must maintain links to fast‑moving satellites, cope with platform motion and interference, and still hit tight power and cost targets. This makes the beamforming silicon architecture a critical design choice. EnSilica’s experience in custom beamforming ASICs for satellite user terminals and wider communications systems directly targets these design constraints.

Why hybrid beamforming silicon matters

A purely analogue array keeps RF hardware compact and power efficient, with phase shifters and gain control close to each antenna element and signals combined in RF. That approach can work for relatively narrowband, slowly changing links, but it struggles once bandwidths grow and interference becomes significant, because beam squint, limited calibration options and weak visibility into the received wavefield start to dominate.

A fully digital array takes the opposite route by digitising every element, enabling multi‑beam operation, adaptive nulling and sophisticated spatial algorithms. The downside is the number of high‑speed converters, clocks and digital channels required at Ku/Ka‑band, which can make power, thermal design and integration impractical for mass‑market terminals.

Hybrid beamforming ASICs provide a pragmatic middle ground. You retain a short, efficient analogue beamforming path at sub‑array level, while moving higher‑level beam shaping and interference mitigation into a smaller set of digital channels. This reduces converter count and power compared with a fully digital array, yet offers far more beam control and observability than a simple analogue design.

Partitioning the phased array

In a hybrid architecture, the aperture is divided into tiles. Each tile typically contains a cluster of radiating elements, one or more analogue beamformer ICs and a digital beamformer device.

• The analogue beamformer ASIC handles per‑element phase and amplitude and combines elements into sub‑arrays.
• The digital beamformer ASIC operates on the digitised outputs of those sub‑arrays rather than on individual elements.

The number of elements feeding each digital channel – the hybrid ratio – is a key design lever. Low ratios provide finer spatial resolution and more powerful interference mitigation; higher ratios cut converter count, data rate and power. For mass‑market user terminals, practical ratios usually sit between a few elements per converter and a few dozen elements per converter, depending on link budget, interference environment and cost targets.

This tiling approach simplifies manufacturability. RF routing remains local and predictable within a panel, and tiles can be replicated to scale array size without redesigning RF distribution each time. In practice, that lets you scale a terminal family by re‑using the same beamforming silicon and tile design across multiple apertures.

Local frequency generation and array coherence

For wideband OFDM waveforms in 5G NTN and high‑order modulation at Ka‑band, array‑level phase noise and coherence matter as much as individual PLL datasheet numbers. If phase errors drift across the aperture, coherent gain is lost, beam pointing degrades and nulls become shallow, while EVM and spectral regrowth worsen.

Hybrid beamforming silicon addresses this by generating high‑frequency local oscillators locally in each tile or sub‑array. Instead of distributing a Ka‑band local oscillator (LO) across the entire panel, a lower‑frequency reference is distributed and multiplied on‑tile with integrated PLLs. This keeps LO traces shorter and less exposed to parasitics and temperature gradients.

Because the phase‑noise contributions of multiple local PLLs are largely uncorrelated, their outputs average down when combined coherently across the array. Simulations in the source work show that by distributing synthesis across multiple low‑power PLLs, it is possible to meet demanding broadcast‑grade phase‑noise limits at array level while cutting PLL power by around 80% compared with a single high‑performance COTS device. If you are architecting the silicon, this favours integrated PLLs per tile or per sub‑array, robust reference distribution and facilities to monitor and trim local oscillators in the field.

Role of the digital beamformer

On the receive path, each sub‑array output appears as a virtual element to the digital beamformer. The number of digital channels is much smaller than the number of physical elements, but still sufficient to retain useful spatial information. With K digital channels, the system can typically separate the desired signal from up to about K–1 significant interferers in realistic user terminal scenarios.

On this reduced‑dimension data, the digital processing chain can perform:

• Initial direction finding and beam acquisition.
• Fine beam tracking under platform and satellite motion, often combining direction‑of‑arrival estimates with simple error‑sensing schemes.
• Detection and localisation of interference sources, followed by adaptive beamforming to place nulls where they provide the most benefit.

In many designs, classical direction‑of‑arrival algorithms are simplified and constrained using prior knowledge of satellite geometry to keep processing and memory demands under control. Increasingly, deterministic algorithms are combined with lightweight ML‑based estimators to stabilise performance at low SNR or under imperfect calibration, without adding RF complexity. For your SoC or ASIC, that points towards programmable beamforming engines, flexible coefficient storage and interfaces that allow higher‑level software to steer algorithms and update weights independently of the RF front‑end.

Calibration as a built-in system function

In highly integrated phased arrays, gain, phase and timing errors vary with temperature, operating state and ageing, so calibration cannot be treated as a one‑time production step. It has to be implemented as a repeatable system function that runs throughout the terminal’s lifetime.

Hybrid architectures make this more tractable. Keeping RF paths local within tiles reduces variation and drift compared with long, distributed analogue networks, improving inherent stability. At the same time, digital channels at sub‑array level provide enough observability to estimate and correct relative errors without digitising every element.

In practice, calibration flows combine on‑chip test modes with over‑the‑air procedures that use known signals from the network to keep the array aligned over time. Supervisory algorithms, including ML‑based approaches, can learn slow drift behaviour and update correction tables in the background, reducing recalibration frequency and helping maintain performance over temperature and ageing. Beamforming ASICs therefore benefit from embedded calibration engines, access to key internal nodes and stable reference‑distribution schemes.

Implications for LEO and 5G NTN terminals

LEO constellations and 5G NTN specifications share several traits: rapid motion, wideband OFDM waveforms, frequent beam updates and crowded spectrum. These conditions make it difficult for a purely analogue array to maintain performance and push fully digital arrays beyond realistic power and cost limits for user equipment.

Hybrid phased‑array beamforming ASICs offer an architecture that aligns well with this environment. Local analogue beamforming keeps the RF front‑end compact and efficient, while digital control across sub‑arrays provides sufficient beam agility and spatial awareness for link acquisition, tracking and interference mitigation. Local frequency generation helps maintain array coherence without extreme PLL power budgets, and tile‑level calibration keeps performance stable over time and temperature.

For teams designing next‑generation satellite user terminals, this hybrid ASIC approach provides a practical way to meet LEO and 5G NTN requirements without resorting to either oversimplified analogue technology or impractical, fully digital architectures. EnSilica’s application‑specific products for satcom user terminals apply these hybrid phased‑array concepts in silicon, covering both Ka‑ and Ku‑band beamforming devices. Where standard beamforming ICs are not an exact fit, EnSilica’s turnkey ASIC services enable OEMs to implement hybrid beamforming architectures as fully custom devices, while managing design, verification and supply chain as a single programme.

A growing opportunity for EnSilica and its novel 3-in-1 post-quantum cryptography silicon…

EnSilica, a leading maker of mixed-signal ASICs (Application Specific Integrated Circuits), has developed a combined hardware IP block supporting the full CRYSTALS post-quantum cryptography (PQC) suite, saving silicon area, power and cost. The licensable eSi-CRYSTALS PQC accelerator runs Dilithium (FIPS-204), Kyber (FIPS-203) and SHA-3 (FIPS-202) algorithms, which previously required three separate IP blocks.

In August 2024, the US National Institute of Standards and Technology (NIST) released the first three finalised PQC standards, with additional algorithms announced or in draft stages. Dilithium, Kyber, and SHA-3 are advanced cryptographic algorithms designed to secure digital systems against both classical and quantum computing threats. Dilithium is used for digital signatures, providing authentication and data integrity, while Kyber is a key encapsulation mechanism that enables secure key exchange. Integrated into the block is also a hardware-optimised implementation of the cryptographic SHA-3 hash function that creates a digital fingerprint of data allowing for robust integrity verification. Together, these algorithms form the foundation for quantum-resistant security in modern systems, ensuring long-term protection of sensitive information.

Ian Lankshear, CEO of EnSilica, commented:

“The emerging PQC threat is not just theoretical. Security analysts warn that adversaries can already capture encrypted data today, with the intention of decrypting it in the future when quantum capabilities become available, a tactic known as ‘harvest now, decrypt later’. The implications are profound for those relying on today’s cryptographic schemes, which is why EnSilica’s PQC offering delivers future-proof hardware protection at the silicon level with minimal silicon area for mature and advanced technology nodes.”

EnSilica previously announced separate Dilithium, Kyber and SHA-3 algorithms licensed for use by a major semiconductor company for a 5 nm networking ASIC. The new IP offers a more compact implementation than separate cores. EnSilica also has a full suite of classical cryptographic accelerators including ECC, ECDSA, RSA, AES, ChaCha20, and Poly1305. In addition, the company offers a NIST-compliant true random number generator (TRNG).

23rd June 2026

Year End Trading Update

 A record trading year, major contract wins and fast growing sales pipeline

FY27 revenues of £32-34m already 80% covered underpinning further growth 

EnSilica plc (AIM: ENSI), a leading fabless microchip maker with a growing portfolio of reusable IP, serving the Space and Communications, Industrial, and Automotive markets, is pleased to announce the following update on the Group's trading performance for the financial year ended 31 May 2026 ("FY26"). The financial information contained in this announcement is unaudited and remains subject to completion of the Group's year-end audit. 

The Company expects to announce record results showing substantial trading growth over the prior year on all key metrics, a significantly enhanced balance sheet following an oversubscribed £10m equity fundraise in March 2026, and an expanded new business sales opportunities pipeline, up by $200m to $600m (even after $125m of contract wins transferred from the pipeline into supply revenues).  Overall, the results reflect the progress of the Group's continued transition from being a design-led business to becoming a semiconductor design-and-supply company. 

Year ended 31 May	FY26 Unaudited	FY25 Audited	Change
Revenue	£27.5m	£18.2m	51%      ↑
EBITDA	£4.7m	£2.0m	£4.7m     ↑
Lifetime Supply Revenues	$375m	$250m	50%     ↑
Sales Opportunities Pipeline	$600m	$400m	50%     ↑

Commenting on the FY26 trading performance, CEO Ian Lankshear, said:

"FY26 has been a very successful year for the Group as it continues in its transition to being a fabless semiconductor company. As these results show, we believe the business has moved to the next stage in becoming a leading, scalable platform in chip design and manufacturing within our specialist high-growth markets, especially the rapidly expanding Space and Communications sector. We have proven our capabilities in the marketplace and the £10m equity fundraise in March 2026 to strengthen our balance sheet has enabled the Company to make material strategic progress, including securing two satellite contracts with the potential to unlock matched funding and a strategically important $75m auto contract.

With the excellent contract conversion we enjoyed during FY26, the success of our model is increasingly evident, now with 3 chips poised to boost revenues by moving into supply production over the next 18 months. Moreover, the 50% increase in our lifetime supply revenues and new business pipeline to $375m and $600m respectively is an indication of the future trajectory of the business and EnSilica's ability to achieve its ambition of becoming a global leader in chip design and manufacture. The Company has never had a stronger pipeline of opportunity and management are now focused on evolving our repeatable IP into long-term revenue-generating chips which current and future customers will rely on for years to come." 

FY26 Trading

The Company expects to deliver revenues of £27.5m for FY26, which are within 2% of the £28-30m guidance. Pleasingly, the anticipated EBITDA of £4.7m exceeds guidance of £3.5-4.5m, enhanced by Space related grant income. On 11 June 2026, shortly after the year end, the Company announced the completion of the tape-out stage for the Edge AI contract, which had originally been forecast to occur during FY26 and instead it bridged into the new financial year.  Had the tape-out for the Edge AI contract occurred within FY26, revenues would have been ahead of market expectations. 

Looking forward, the Group expects FY27 revenues to be in the range of £32-34m and EBITDA of £5.5-6.5m, reflecting the Group's strengthened visibility against prior years, as approximately 80% of anticipated FY27 revenues were already covered at the start of the financial year by existing contracts, supply agreements and customer orders.  For comparison, the Company announced approximately 80% coverage of its FY26 revenues as part of its full year results in November 2025.

In addition, the Company has also completed the tape-out stage of a second ASIC for Siemens for use in industrial automation, which is on schedule to be in production in FY27.

Current lifetime supply revenues increased by 50% to $375m compared to $250m at the outset of the financial year, with the uplift coming primarily from two major contract wins: a user terminal chipset programme with a leading European satellite operator, expected to generate lifetime semiconductor supply opportunities exceeding $50m, and a major automotive semiconductor supply contract, expected to generate approximately $75m over its lifetime. 

The expansion of the new business sales pipeline, increasing from $400m to $600m (even after $125m of contract wins transferred from the pipeline into supply revenues), comprises potential customers from across our core target sectors. These include high-value satellite payload projects for major operators and manufacturers, which are already at either the funded-study or first-phase design stage, as well as several key opportunities for EnSilica's proprietary user satellite terminal ASSPs.  

Cash at year end was £7.5m. This strengthened financial position has enabled the Company to accelerate and broaden its commercial activities, and together with growth in both supply and NRE revenues and the growing sales pipeline, the Board will continue to invest in strengthening the pipeline and accelerating the conversion of opportunities to enhance returns over the longer term, whilst also targeting positive monthly operational cash generation after investment in intangible assets, and therefore now expected by the end of FY27.  

The success of EnSilica's business model is increasingly evident with the Company's portfolio of chips visibly maturing, moving from design stage into generating long-term supply revenues. The Group currently has five ASICs in the volume supply phase, with several additional programmes expected to enter volume supply during FY27 and FY28. Alongside this progress, it is notable that EnSilica has yet to fully realise the financial benefits of its position in the high-value space sector. Currently, only one chip is generating supply revenues, while a further five of the Company's 14 chips in design are targeted at Space applications. As these programmes move into production, they are expected to become significant contributors to future revenue growth.

Outlook

Demand for EnSilica's specialist expertise remains strong across its Space & Communications, Industrial and Automotive markets. With strong revenue visibility, an expanding production portfolio, growing semiconductor supply revenues and record levels of long-term supply opportunities, the Board remains confident in the Group's growth trajectory and future profitability.

Notice of Results

The Company expects to announce its audited results for the year ended 31 May 2026 in October 2026.