I Implemented the TIS-100 Architecture on my Atum A3 Nano
If you haven't heard of this game, you should definitely check it out. It is awesome.
I was playing it recently and it occurred to me that I could absolutely design the architecture in VHDL, so I took a swing at it. This is a short demo of some very simple functionality actually running on the board (this is very much still a WIP).
I realize this UI is disgustingly hideous. I just wanted to throw something together so I could actually test it out. I plan to eventually actually interpret the assembly commands, I just didn't feel like spending the time to do that before I actually got to run it.
Each outer core has a shallow input and output fifo. There is a UART controller that can parse messages to write instructions to each core, enable/disable execution, and write data to the input fifos. It also monitors the occupancy of each output fifo, and sends a message with the direction, index, and data of the values coming out of the cores. You can see, at the bottom of the UI, it is sending out incrementing values.
So, this UI is converting these instructions into UART messages and programming each core of the device. It is also reading from the UART and interpreting the messages as direction, index, and data (hence up[0]: x)