▲ 4 r/esp32projects+1 crossposts

Title: Building a DIY Smart Glass with ESP32-C6 — Looking for Advice on Audio, Mic & Power Design

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Hi everyone,

I'm working on a DIY smart glasses project and would really appreciate some guidance from people who have experience with ESP32, embedded audio, wearable electronics, or similar projects.

Current hardware plan

MCU: ESP32-C6

Speaker: Bone-conduction speaker

Microphone: MEMS microphone

Rechargeable battery

Custom PCB eventually, after validating the prototype

The basic idea is to build a lightweight smart-glass platform that can eventually support things like voice interaction, audio notifications, and potentially on-device/edge AI features.

Right now I'm mainly trying to get the hardware architecture right before designing the PCB.

Things I'm unsure about

  1. Microphone I'm currently looking at digital MEMS microphones with I2S/PDM interfaces.

Which microphone would you recommend for a wearable application?

Is PDM preferable to I2S for this kind of design?

How should I handle microphone placement to reduce wind/ambient noise?

  1. Bone-conduction audio I'm planning to use a bone-conduction transducer.

What type of amplifier/driver should I use with ESP32-C6?

Are there any particular audio codecs/DACs that make sense here?

How difficult is it to get good voice-quality audio while keeping power consumption low?

  1. Audio processing For the microphone side, I'm considering things such as:

DC offset removal

High-pass filtering

Noise suppression

Automatic gain control

Voice activity detection

Beamforming, if I eventually use multiple microphones

I'd appreciate advice on what processing is actually practical on an ESP32-C6 and what should instead be handled externally/cloud-side.

  1. Bluetooth / connectivity The glasses will probably communicate with a phone for some functions.

Would you recommend keeping the ESP32-C6 as the main controller, or is there a better ESP32 variant for a project like this considering Bluetooth audio, memory, processing capability and power consumption?

  1. Power Since this will be worn on the face, battery life and size are very important.

What would be a realistic target for:

Battery capacity

Average power consumption

Charging IC

Voltage regulation

Expected runtime

I'd especially appreciate advice from anyone who has built wearable audio devices, smart glasses, Bluetooth audio devices, or ESP32-based voice interfaces.

I'm still at the architecture/prototyping stage, so I'm very open to changing components if there is a significantly better approach.

Thanks!

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u/Logical_Extension331 — 2 months ago
▲ 25 r/vlsi

Intern Life

Umm, so i joined a start up as a design and verification Intern and now they don't give me any briefs like how everything works and all . They just told me to do linting and fix the warnings which is very boring and monotonous.

The pay is very less and i sit in the office for 11 hours straight as the manager makes me sit for long hours .

So no social life too.

Don't know what to do.

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u/Logical_Extension331 — 5 months ago
▲ 2 r/Verilog+1 crossposts

Does verilator , find combinational loops , i mean i tried it on a .sv file and it finds them through UNOPTFLAT but when i try to run it on bigger files I doesn't catch them any suggestions.

+ I need to force include a .vh verilog header file, how to do it?

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u/Logical_Extension331 — 5 months ago

I have to work on the linting process.

I have 3 files top.v submodule.v and .vh file which is a library header and contains all defines .

And this .vh is placed in a different folder.

There is a Make file , that calls the .pl file to generate .v files and 1 make file calls the verilator and lints the .v

The issue I am facing is that the verilator couldn't find my .vh file although i have mentioned in my assets.vc(which contains all the paths).

As a result i have to use all the DEFINE inside assets.vc and that works which I don't want to do any solutions to it.

Second is if I write the entire path of top.v and submodule.v it works if i give relative path with -y it becomes unable how to solve it.

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u/Logical_Extension331 — 5 months ago

So i am an Electrical undergrad and I got a chance to be an intern in a pcie start up company on the second day they put me on linting and debugging codes I don't know what to do. No much senior help they said reverse engineer

I have basic understanding in verilog systemverilog and digital electronics. What to do?

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u/Logical_Extension331 — 6 months ago