u/LopsidedSafe6632

I have completed SystemVerilog and UVM basics, and I'm currently exploring UVM further. Based on my research on websites like Verification Guide and Chip Verify, the theories presented differ slightly, even though the topics cover the same material.

1. The verification guide website felt beginner-friendly to intermediate, making it easy to learn and practice.

2. Chip verify seems to require an intermediate to advanced level of SystemVerilog, and even after covering the basics in my UVM training, I struggled to understand it. I spent nearly three weeks on SystemVerilog, but the concepts were still beyond my comprehension. I'm unsure if the expected level of UVM expertise on the Chip verify website is genuinely necessary.

I'd appreciate any recommendations for resources to help me learn UVM concepts. Are there any playlists, books, or other materials that might be helpful? I'm particularly interested in trying out books, but I find reading them time-consuming, so I'm open to other suggestions.

Would any of you parallel learners or those preparing for DevOps be willing to chat about the complexity and depth of the UVM concepts? I'm interested in collaborating and learning more. Additionally, could you provide some general guidance on the typical level of in-depth understanding required for UVM concepts?

I have completed SystemVerilog and UVM basics, and I'm currently exploring UVM further. Based on my research on websites like Verification Guide and Chip Verify, the theories presented differ slightly, even though the topics cover the same material.

1. The verification guide website felt beginner-friendly to intermediate, making it easy to learn and practice.

2. Chip verify seems to require an intermediate to advanced level of SystemVerilog, and even after covering the basics in my UVM training, I struggled to understand it. I spent nearly three weeks on SystemVerilog, but the concepts were still beyond my comprehension. I'm unsure if the expected level of UVM expertise on the Chip verify website is genuinely necessary.

I'd appreciate any recommendations for resources to help me learn UVM concepts. Are there any playlists, books, or other materials that might be helpful? I'm particularly interested in trying out books, but I find reading them time-consuming, so I'm open to other suggestions.

Would any of you parallel learners or those preparing for DevOps be willing to chat about the complexity and depth of the UVM concepts? I'm interested in collaborating and learning more. Additionally, could you provide some general guidance on the typical level of in-depth understanding required for UVM concepts?

I have completed SystemVerilog and UVM basics, and I'm currently exploring UVM further. Based on my research on websites like Verification Guide and Chip Verify, the theories presented differ slightly, even though the topics cover the same material.

1. The verification guide website felt beginner-friendly to intermediate, making it easy to learn and practice.

2. Chip verify seems to require an intermediate to advanced level of SystemVerilog, and even after covering the basics in my UVM training, I struggled to understand it. I spent nearly three weeks on SystemVerilog, but the concepts were still beyond my comprehension. I'm unsure if the expected level of UVM expertise on the Chip verify website is genuinely necessary.

I'd appreciate any recommendations for resources to help me learn UVM concepts. Are there any playlists, books, or other materials that might be helpful? I'm particularly interested in trying out books, but I find reading them time-consuming, so I'm open to other suggestions.

Would any of you parallel learners or those preparing for DevOps be willing to chat about the complexity and depth of the UVM concepts? I'm interested in collaborating and learning more. Additionally, could you provide some general guidance on the typical level of in-depth understanding required for UVM concepts?

I have completed SystemVerilog and UVM basics, and I'm currently exploring UVM further. Based on my research on websites like Verification Guide and Chip Verify, the theories presented differ slightly, even though the topics cover the same material.

1. The verification guide website felt beginner-friendly to intermediate, making it easy to learn and practice.

2. Chip verify seems to require an intermediate to advanced level of SystemVerilog, and even after covering the basics in my UVM training, I struggled to understand it. I spent nearly three weeks on SystemVerilog, but the concepts were still beyond my comprehension. I'm unsure if the expected level of UVM expertise on the Chip verify website is genuinely necessary.

I'd appreciate any recommendations for resources to help me learn UVM concepts. Are there any playlists, books, or other materials that might be helpful? I'm particularly interested in trying out books, but I find reading them time-consuming, so I'm open to other suggestions.

Would any of you parallel learners or those preparing for DevOps be willing to chat about the complexity and depth of the UVM concepts? I'm interested in collaborating and learning more. Additionally, could you provide some general guidance on the typical level of in-depth understanding required for UVM concepts?

Could anyone please provide some information regarding the quality of education and the faculty placements offered in the metallurgy department at MGIT Hyderabad?

Hey everyone,I’m currently at a Tier 3 college and trying to figure out my path. I’m torn between preparing for GATE 2027 or focusing entirely on placements.

Here is my current situation:

College/Placements: My college is Tier 3. Typical placements are average service-based companies (TCS, Wipro, etc.).

Skillset: I actually enjoy the core side. I’m good at Digital Electronics, Verilog, and SystemVerilog. I’m currently learning UVM and have some experience with EDA tools.

The Dilemma: I know I can likely land a job at a service-based firm, but I really want to get into a top-tier product company or a solid VLSI role.

If I start preparing for GATE now, is a top rank realistic from a Tier 3 background? Or should I double down on my Verilog/UVM skills to try and find a better off-campus core job?Would love to hear from anyone who chose M.Tech to pivot from Tier 3, or those who made it into VLSI without GATE. Is the M.Tech tag from an IIT/NIT worth the 2-year prep and degree time?Thanks!

Hey everyone,I’m currently at a Tier 3 college and trying to figure out my path. I’m torn between preparing for GATE 2027 or focusing entirely on placements.

Here is my current situation:

College/Placements: My college is Tier 3. Typical placements are average service-based companies (TCS, Wipro, etc.).

Skillset: I actually enjoy the core side. I’m good at Digital Electronics, Verilog, and SystemVerilog. I’m currently learning UVM and have some experience with EDA tools.

The Dilemma: I know I can likely land a job at a service-based firm, but I really want to get into a top-tier product company or a solid VLSI role.

If I start preparing for GATE now, is a top rank realistic from a Tier 3 background? Or should I double down on my Verilog/UVM skills to try and find a better off-campus core job?Would love to hear from anyone who chose M.Tech to pivot from Tier 3, or those who made it into VLSI without GATE. Is the M.Tech tag from an IIT/NIT worth the 2-year prep and degree time?Thanks!

Hey everyone,

I’m currently at a Tier 3 college and trying to figure out my path. I’m torn between preparing for GATE 2027 or focusing entirely on placements.

Here is my current situation:

College/Placements: My college is Tier 3. Typical placements are average service-based companies (TCS, Wipro, etc.).

Skillset: I actually enjoy the core side. I’m good at Digital Electronics, Verilog, and SystemVerilog. I’m currently learning UVM and have some experience with EDA tools.

The Dilemma: I know I can likely land a job at a service-based firm, but I really want to get into a top-tier product company or a solid VLSI role.

If I start preparing for GATE now, is a top rank realistic from a Tier 3 background? Or should I double down on my Verilog/UVM skills to try and find a better off-campus core job?Would love to hear from anyone who chose M.Tech to pivot from Tier 3, or those who made it into VLSI without GATE. Is the M.Tech tag from an IIT/NIT worth the 2-year prep and degree time?Thanks!

Hi everyone,

I’m an ECE student and I want to become a Design Verification (DV) engineer.

I already know Verilog, digital electronics, and a bit of physical design basics. Now I want to move into SystemVerilog and UVM.

Just wanted to ask:

What topics should I focus on next?

How much SystemVerilog and UVM is enough?

Any good courses or certifications worth doing?

What tools should I learn?

What kind of projects should I build?

What do DV engineers actually do day to day?

My goal is to get into a good product-based company in the next 1–2 years.

Any advice or roadmap would really help 🙏

Thanks!

Hi everyone,

I’m an ECE student and I want to become a Design Verification (DV) engineer.

I already know Verilog, digital electronics, and a bit of physical design basics. Now I want to move into SystemVerilog and UVM.

Just wanted to ask:

What topics should I focus on next?

How much SystemVerilog and UVM is enough?

Any good courses or certifications worth doing?

What tools should I learn?

What kind of projects should I build?

What do DV engineers actually do day to day?

My goal is to get into a good product-based company in the next 1–2 years.

Any advice or roadmap would really help 🙏

Thanks!