Process gases for Cryogenic etch
Cryogenic etching represents the most significant paradigm shift in dielectric etch technology since the transition from wet to dry processing. Driven by the need to etch channel holes exceeding 400 layers in 3D NAND, the industry has converged on a class of process technology that operates at substrate temperatures of negative tens of degrees Celsius — a regime that would have seemed impractical for production dielectric etch a decade ago.
This chapter explains why cryogenic temperature is the enabling variable that makes this class of chemistry work, details the surface reaction mechanisms understood for hydrogen fluoride (HF) based cryogenic etching, examines the two competing technology platforms that have brought cryogenic etching into high-volume production, and assesses the supply chain and environmental implications of this still-rapidly-evolving process category. Readers approaching this chapter after Section 2.6 (gas-phase HF) and Chapter 4 (argon) will find the foundational gas properties already established; this chapter focuses on what changes when these gases are deployed in the cryogenic thermal regime.
A note on sources for this chapter: cryogenic etching is among the newest and most competitively guarded process technologies in semiconductor manufacturing. Tokyo Electron (TEL) has been comparatively open in publishing its underlying chemistry — including HF and phosphorus-containing gas species — through peer-reviewed conference proceedings (AVS, VLSI Symposium). Lam Research, by contrast, has not publicly disclosed the specific gas chemistries used in its Cryo platform; industry reporting confirms only that Lam's three successive cryogenic etch generations have each used different chemistries, without specifying which gases. Where this chapter describes TEL's HF-based chemistry in mechanistic detail, that detail is grounded in TEL's own published technical disclosures. Where Lam's specific chemistry would be required to make an equivalent mechanistic claim, this chapter says so explicitly rather than assuming parity with TEL's disclosed approach.
6.1 Why Temperature Changes Everything
The Limits of Room-Temperature Fluorocarbon Chemistry
The fluorocarbon-based dielectric etch chemistry described in Chapter 2 — C₄F₈, C₄F₆, CHF₃, and related gases — has scaled remarkably well for three decades, but it faces a fundamental physical limit at the aspect ratios now required for advanced 3D NAND structures exceeding 400 layers. As channel hole aspect ratio increases, two related problems intensify: aspect-ratio-dependent etching (ARDE), where etch rate declines as the feature deepens because reactant transport to the bottom of the hole becomes diffusion-limited, and sidewall bowing, where the fluorocarbon passivation layer becomes increasingly difficult to maintain uniformly along the full length of an extremely narrow, deep channel. Patent literature describing cryogenic dielectric etch approaches notes specifically that at cryogenic temperatures, the large fluorocarbon fragments from C₄F₆ and C₄F₈ tend to become stuck near the top of a high-aspect-ratio feature and block the etch front, rather than reaching the bottom — meaning conventional room-temperature fluorocarbon chemistry does not simply transfer to a cryogenic chuck without reformulation.
These problems are not solvable by further fluorocarbon chemistry optimization alone — they are consequences of the fundamental physics of neutral species transport and ion trajectory control in extreme-aspect-ratio features. A different physical regime is required, and cryogenic substrate temperature is the variable that provides it.
Thermodynamics of Surface Adsorption at Cryogenic Temperatures
The behavior that makes cryogenic etching possible is rooted in basic adsorption thermodynamics. The residence time of a gas molecule adsorbed on a surface increases as temperature decreases, following an Arrhenius-type relationship governed by the desorption activation energy. At room temperature, gas-phase HF molecules striking a SiO₂ surface have a short residence time before thermal desorption — as established in Section 2.6, conventional vapor-phase HF (VHF) etching requires a co-reactant (water vapor or methanol) acting as a surface initiator for the HF/SiO₂ reaction to proceed at a useful rate.
At cryogenic substrate temperatures — TEL has disclosed operating in a range of negative tens of degrees Celsius for its production cryogenic etch process — this picture changes. Longer HF surface residence time allows greater surface coverage and reaction time, and patent and conference literature describing cryogenic dielectric etch processes indicate that fluorine sources capable of generating atomic or near-atomic fluorine species — including HF — are favored over large polymerizing fluorocarbon molecules precisely because the small fluorine-bearing species can reach the bottom of an extreme-aspect-ratio feature where the large fluorocarbon fragments cannot.
Suppression of Isotropic Chemical Etching
A second consequence of cryogenic temperature, understood at a general mechanistic level across the cryogenic etch literature, is the suppression of spontaneous, isotropic chemical etching that would otherwise compete with the desired anisotropic, ion-driven etch mechanism. At cryogenic temperatures, the etch chemistry is structured so that material removal proceeds efficiently only where directional ion bombardment activates the surface — at the feature bottom — while the sidewall, shielded from direct ion bombardment, is comparatively protected. The general principle, described in patent literature on cryogenic dielectric etch chemistry, is that different elements serve different roles at cryogenic temperature than they do at room temperature: species effective for etching silicon, oxygen, or nitrogen components of a stack, and species effective as passivating agents, are not always the same as their room-temperature counterparts.
Formation of Stable Passivation Layers on Sidewalls
The third critical temperature-dependent effect concerns sidewall passivation. Conventional room-temperature fluorocarbon processes (Section 2.4) rely on a thick, chemically robust (CF₂)ₙ polymer film to protect sidewalls through mechanical and chemical resistance to lateral fluorine attack. At cryogenic temperatures, a qualitatively different passivation paradigm becomes accessible: species that would be too weakly bound to persist as a stable passivation layer at room temperature can remain adsorbed for the duration of the etch step simply because desorption is thermally suppressed. This is the general mechanism by which TEL's published PHastIE process — Phosphorus and Hydrogen-based Fast Ion Etch — is understood to operate, using a phosphorus-and-hydrogen-containing gas chemistry alongside HF to achieve sidewall protection without the thick polymer films of conventional Bosch-type or HARC processes (Section 2.4).
Comparison with Conventional Fluorocarbon Chemistry
| Parameter | Conventional Fluorocarbon (Room Temp.) | Cryogenic Dielectric Etch (General) |
|---|---|---|
| Operating temperature | 0°C to 60°C | Negative tens of degrees Celsius |
| Typical fluorine source | C₄F₈, C₄F₆ (large polymerizing fragments) | Small F-bearing species (e.g., HF) favored for bottom-of-feature transport |
| Sidewall passivation | Thick (CF₂)ₙ polymer film | Thinner, temperature-stabilized passivation layer (chemistry vendor-specific) |
| Practical aspect ratio target | ~40–50:1 | 3D NAND channel holes for 400+ layer stacks |
| ARDE sensitivity | High at extreme AR | Reduced — primary value proposition of the technology |
Table 6.1 General comparison of conventional room-temperature fluorocarbon etching and cryogenic dielectric etching
Section Notes
1 U.S. Patent Application 2023/0187234, Plasma Etching Chemistries of High Aspect Ratio Features in Dielectrics, Lam Research Corporation.
2 U.S. Patent Application 2021/0005472, Plasma Etching Chemistries of High Aspect Ratio Features in Dielectrics, Lam Research Corporation.
3 Tokyo Electron Ltd. Cryogenic Etching — Tokyo Electron's Digital and Green Transformation of Semiconductor Process Equipment. Company blog, October 2024.
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