How long will take us as a nation to reach this level of manufacturing capabilities?
Mind you, this the missile was made in 1960! Imagine at that time, how our industry was? Probably very basic if any!, with the post-war/ post-indpendence situation and all ....
Hello All,
I did this test 3 years ago, I was able to use the Yseq cladefinder using MyHeritage raw data, but I can't do it anymore for some reason.
I used the MorleyDNA Subclade Predictor also, and it shows similar results.
I think my results are very common within the Arab clans in Algeria. The previous version of the Ethnicity estimate used to show 20% Iberian and no Egyptian!
Probably in the near future, I will do a full yseq test for more in-depth paternal lineage.
Y'all have a nice day.
Hey everyone,
I recently came across some T-type leg modules (see images), each one packs 4 MOSFETs into a single package, making them a good building block for multilevel topologies. I'm planning to use three of them to build a 3-phase, 3-level T-type NPC inverter, but I'm hitting a wall when it comes to the PCB layout.
My main struggle is routing the power traces (polygons). With three legs sharing a split DC bus and a common neutral point, the copper pours are getting crowded fast, and I'm not sure how to cleanly separate the high-current paths without creating huge loops or thermal hotspots.
To keep things manageable, I've decided to move the gate drivers to a separate top-mounted daughter board rather than cramming the gate signals onto the power board. That should help isolate the switching noise from the power planes, but I'd love to hear if anyone has done something similar and whether that approach caused any new headaches (signal integrity, connector placement, etc.).
Also how would you approach the power polygon routing in this scenario, given 6 layers?
Any tips on minimising the DC bus loop inductance?
how i initially planned to plac the 3 modules.
Thank you,
Hello everyone,
I have a 10V voltage reference (REF5010ID), that is connected to 5x ADTL082ARZ, Dual Operational Amplifier. The 10V reference is connected to a 20k resistor divider (as in picture below). The issue I am having is that I am reading 1.8-ish volt on the output of the REF5010ID !?
I put a 1uF capacitor between TRIM/NR Pin and ground for Noise Reduction as recommended in the datasheet.
Tests i have done so far:
I removed all the 20k resistors (in schm are 200k) and I measured 7.3V !? but it should be 10V !
I thought the chip was damaged, so I took a new REF5010ID, assembled it on my board, and still got 7.3V.
I also took the removed IC from step 2 and wired 2 wires from VIN (pin 2) and GND (pin 4) to a power supply, measured Vout with a DMM and guess what I got 7.3V lol
what am i doing wrong !?
