https://preview.redd.it/bppz5esca6kh1.png?width=710&format=png&auto=webp&s=93a00ec031fa9dbc891d17617edc3e7520619c23

https://preview.redd.it/k26kvt12a6kh1.png?width=940&format=png&auto=webp&s=7e03b9e031623109bf9918741f706bb0f01d97ce

https://preview.redd.it/z3s55ne5a6kh1.png?width=841&format=png&auto=webp&s=ea874f55610212e69b0457910a2336be1916d5bf

https://preview.redd.it/aoogl49da6kh1.png?width=710&format=png&auto=webp&s=262e57835d82c4737fbe063e51d83bccf925b3c0

Hi everyone,

I'm a student working on a DIY digital storage oscilloscope as a project, and I've reached the point where I'd really like an experienced engineer to review the analog front end before I move toward PCB design.

The ADC I'm using is an AD9200 (10-bit, 20 MSPS), and my current target is roughly 5 MHz useful analog bandwidth.

The attached schematic is my current AFE.

Signal chain

Input → selectable attenuator → protection → buffer → bipolar-to-unipolar conversion → 4th-order LPF → ADC-side protection → AD9200

1. Attenuator

I have four selectable ranges:

• 1×
• 5×
• 10×
• 25×

The maximum external input I intend to apply is approximately ±25 V.

I'm using SPDT switching so that only the selected attenuation network is connected to the signal path, preventing the other networks from loading the active path.

I've simulated the frequency response of each attenuation range separately and they appear reasonable over the intended bandwidth.

2. First protection stage

After the attenuation network I have a 220 Ω series resistor and Schottky clamps to the ±5 V analog rails.

The idea is that the attenuation network provides most of the current limiting because of its relatively high resistance, while this stage provides additional protection for the input buffer.

3. Input buffer

I'm using an OPA1652 as a unity-gain buffer.

The purpose is mainly to prevent the attenuator from being loaded by the following circuitry.

4. Bipolar → unipolar conversion

The attenuated/buffered signal is bipolar, but I need a unipolar signal for the ADC.

I'm using a unity-gain offset stage with a +1 V reference, giving approximately:

• −1 V → 0 V
• 0 V → 1 V
• +1 V → 2 V

So the waveform amplitude isn't intentionally changed; it is shifted upward.

5. Anti-aliasing filter

I decided on two cascaded 2nd-order active low-pass sections, rather than going to a more complicated 6th-order filter.

My priority is to keep the response reasonably flat through approximately 5 MHz, while still getting some attenuation of higher-frequency content before the 20 MSPS ADC.

The current simulated response is roughly −0.36 dB at 5 MHz.

I realize this is a compromise between passband flatness and anti-alias rejection, and I'd especially like opinions on whether this is sensible.

6. ADC-side protection

This is the part I'm least confident about.

I'm planning a second protection stage immediately before the AD9200 so that faults downstream of the first protection stage cannot reach the ADC directly.

The main concern is the AD9200 AIN absolute minimum of −0.3 V. I'm trying to design the negative clamp so that the ADC never gets close to that limit, rather than relying on the ADC's internal protection.

I'm considering low-forward-voltage Schottky clamps and a series resistor before AIN.

What I'd really like reviewed

I'd appreciate criticism of the design, especially:

1. Is the attenuator/protection architecture reasonable?
2. Is the bipolar-to-unipolar conversion approach sensible for the AD9200?
3. Is the 4th-order filter reasonable for a ~5 MHz / 20 MSPS oscilloscope, or am I compromising too much?
4. How would you implement the final ADC protection, particularly the −0.3 V limit?
5. Are there any obvious PCB/layout issues or stability problems I'm overlooking?
6. Is there anything here that looks fundamentally wrong before I commit it to hardware?

I'm deliberately posting the actual current schematic rather than a cleaned-up conceptual block diagram, so please feel free to point out anything ugly or questionable.

Thanks in advance. I'm much more interested in finding problems now than discovering them after fabricating the PCB.