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u/dalance1982

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Heliodor: an RVA23-compliant multicore out-of-order RISC-V core
▲ 40 r/RISCV

Heliodor: an RVA23-compliant multicore out-of-order RISC-V core

Heliodor is an open source RISC-V core written in Veryl, a hardware description language. As of now it has:

  • Dual-issue out-of-order execution
  • Scales to 8 cores with a shared L2 cache
  • RVA23-compliant (vector and hypervisor extensions included)
  • Verified on the native Veryl simulator and Verilator (no FPGA yet)
  • Boots Linux both bare-metal and as a guest under a type-1 hypervisor

For anyone interested in the AI-slop angle, full disclosure: the RTL was coded and debugged almost entirely by Claude Code. That's deliberate, the point of this core isn't clean, readable RTL. It's to give my native Veryl simulator a large design to hunt bugs and benchmark performance against. I also meant for it to generate the kind of strange code a human wouldn't normally write, to poke at corner cases in the Veryl compiler.

For those reasons I wasn't originally planning to publicize Heliodor. But once it reached RVA23 compliance, I realized there are very few open source cores that do (XiangShan, its Kunminghu generation, maybe? I might be missing some), and that a working RVA23 core might be worth sharing in its own right. So I figured I'd post it here.

More details in the blog post:

https://veryl-lang.org/blog/heliodor-rva23/

The Veryl and the Heliodor repo:

u/dalance1982 — 12 days ago
▲ 18 r/FPGA+2 crossposts

Veryl simulator: performance comparison with Verilator

I published a blog post about the performance of the new Veryl native simulator.

Veryl is a modern hardware description language as alternative to SystemVerilog. The native simulator is a new execution backend that doesn't go through SystemVerilog: it uses a hybrid Cranelift + GCC pipeline to combine a responsive first run with high throughput on long simulations.

I benchmarked it against Verilator on a Linux boot (~30M cycles) using an OoO RISC-V core written in Veryl. Across all configurations I measured, Veryl was consistently faster than Verilator, by up to 61%.

Please see the blog for the detailed information:

https://veryl-lang.org/blog/veryl-simulator-performance/

u/dalance1982 — 1 month ago
▲ 15 r/FPGA+2 crossposts

I released Veryl 0.20.0.

Veryl is a modern hardware description language as alternative to SystemVerilog. This version introduces type inference, a built-in logic synthesizer, and a SystemVerilog-to-Veryl translator, along with new language and tool features and a few breaking changes.

  • Breaking: type specification on for iterator removed
  • Breaking: $tb::reset_gen now takes a clk port
  • Type inference for let / const / var declarations
  • Introduce gen declaration for generic constants
  • Logic synthesis support (veryl synth) calibrated against open PDKs
  • SystemVerilog -> Veryl translator (veryl translate)

Please see the release blog for the detailed information:

https://veryl-lang.org/blog/announcing-veryl-0-20-0/

u/dalance1982 — 1 month ago