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I am currently working on a project using the VCU108 board, for which I was using the 1G and 10G Ethernet IPs in Vivado.
The IP licenses/access I was previously using have now expired. Instead of renewing the licenses, I would like to know whether it is possible to obtain the Verilog/source code of these IPs so that I can continue working on the project.
is there is any other way to obtain the required Verilog code?
Thank you.
I am preparing for GATE EC 2027 ,TILL now completed 5 subjects , will complete whole syllabus till October to November but it does not include pyq and revision am I making mistake or not ?
I thought, after syllabus completion will do pyq and subject wise mock test then full length mock test ?
And should I start solving aptitude daily like for 30 min to 1 hour ,
I usually get 6 hr daily time to study apart from job
I am preparing for Gate 2027 EC , I have completed 4 subjects and have 7 months till exam . I also do job which is from 10:30 to 17:45 . I manage to study daily 5-6 hours and on weekend about 9 -10 hours .I cannot leave job due to financial reasons but my goal is to get AIR 1 .
Should I also add gym in my daily life and suggest me what am I doing is correct or not. And give me some advice.
Does anyone know in passive Optical Network system , where do they implement firewall at OLT or ONU side or both , and do OLT control ACL rules of ONU side firewall or not ?
Please help me