▲ 2 r/FPGA+3 crossposts

2 days after google 1st round (technical screening)

Hi guys,

Wanted to know by when google usually calls for loop round interviews after having 1st technical screening.

This post if for silicon validation (google)

reddit.com
u/hardoi_ — 3 days ago
▲ 11 r/FPGA+4 crossposts

Google Cloud Silicon Validation Engineer Interview – What Topics Are Typically Covered?

I have a 45-minute technical screen coming up for a Google Cloud Silicon Validation Engineer role.

Background:

3+ years in Silicon Validation at Texas Instruments

Mostly worked on SoC bring-up, ARM Cortex-R52 based systems, flash/memory subsystems, validation and debug

The recruiter mentioned that the interview generally covers:

Programming basics

SoC architecture

Caches

Page tables / virtual memory

Memory transactions

Performance analysis

Silicon debug

For anyone who has interviewed for Google silicon validation roles recently (or has been an interviewer):

How architecture-heavy was the interview?

Were there deep cache/TLB questions?

How much digital design (CDC, setup/hold, FSMs, etc.) was asked?

Were there debugging scenarios or root-cause analysis questions?

How much Python coding was expected?

Any insights on topics that surprised you or areas I should prioritize would be greatly appreciated.

reddit.com
u/hardoi_ — 12 days ago
▲ 14 r/Semiconductors+3 crossposts

Google Silicon Validation (TPU) Interview in 2 weeks

Hey feed,

Wanted to know some tips if anyone has any experience facing this interview or work in google at this designation.

reddit.com
u/hardoi_ — 25 days ago