Standard milestone flow for Lint, CDC, and Synthesis? (P0.3 to P1.0)
I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.
Here is how I understand the flow:
P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.
P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.
P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.
P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.
My questions:
Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?
At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?
Thanks in advance