How do we define XOR mask for multi-lane bitwise AEGIS AEAD?

I've been inspecting bitwise AEAD implementation and initialization function of the x2-lane variant using XORing by some constant_ctx_mask before every single round. According to the docs on AEGIS, the mask is used to prevent data association from parallelism, but I don't understand why the mask is the way it is.

Let's consider 2 examples:

> Bitwise AEGIS256x2 barrel-shift-32-bit: the mask contains 64 32-bit words set to zero except for positions 30, 61 and 62 with values 0x1F (indexes 29, 60 and 61 correspondingly)

> Bitwise AEGIS256x2 barrel-shift-64-bit: the mask contains 32 64-bit words set to zero except for word 29 set to 0x1F and word 30 set to 0x1F_00_00_00_1F (byte separation by underscores for readability, indexes 28 and 29 respectively).

My questions are:

  1. What's the logic behind building such a mask and reasoning behind such particular values and positions?

  2. How do we extend ithe mask for massive parallelism on e.g. 4-way, 8-way, etc.?

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u/Salat_Leaf — 2 days ago

Difference between unary & and __getAddress in Slang shader?

I'm working on some code and unable to take the address of a "ConstantBuffer" object. However it's allowed with the latter intrinsic. What's the difference between them?

To bring context, my task is to take a ConstantBuffer structure, and reinterpret it as a uint16_t pointer. I can't get around it since I have to take an address of the structure first and then the value itself with the subscript [] operator (that's the only way to create a portable constexpr array of uint16_t constants).

reddit.com
u/Salat_Leaf — 11 days ago

Is there a REALLY fast way of generating randomness with probability padding?

Basically, I have a program that assumes the probability of getting >16 same bits in a row = 0. Is there a very fast way to generate non-secure randomness with condition that probability of sequence of more than n bits must be 0 (thus the next bit must be opposite)? Maybe something like race condition?

reddit.com
u/Salat_Leaf — 14 days ago

Is ML-KEM not truly constant time?

I've been reviewing some of the CUDA source code within the ICICLE library and what caught my attention was the usage of memcpy in the function "byte_encode_compress" with a generic parameter d. The packed coefficients might go up to 96 bits, thus requiring SIMD GPU support for constant time execution. This function is used for ciphertext encoding, so this seems really weird.

Is there a thing I'm missing? Could someone please explain why such a decision was made?

reddit.com
u/Salat_Leaf — 14 days ago

I got 2 evo valks in a row from 2 5-star chests

just in case, these are 2 different screenshots, and the painful fact is that I already got one. The first one is on July 30th, the second one just ago.

:_(

u/Salat_Leaf — 17 days ago

What's the __constant__ equivalent in Slang?

I'm a complete novice in graphics programming and I know that the __constant__ attribute allows you to load data into high speed 65KB constant memory for the duration of the lifetime of your program. However I'm unable to recreate the same functionality in Slang shader.

For instance, we got a compile-time array with the attribute like this:


__constant__ uint16_t array = {0, 1, 2, 3};

I want to recreate it in some way, so that when I compile the same array in Slang into CUDA, it results into this exact array of constant values with the __constant__ attribute. How can I achieve that?

reddit.com
u/Salat_Leaf — 21 days ago

NVIDIA NIM abruptly cuts off responses

I need help. So I connected to NVIDIA NIM successfully (to be precise, GLM-5.2) and everything is working well, it utilizes tooling, responds correctly, however what I've noticed is if you leave it running, at around 110-160k tokens it will get interrupted and return no response. I have an extension in VSCode that lets me connect to OpenAI compatible providers and integrate the models into Github copilot chat. What I have been receiving is "Sorry, no response was returned" after recovery from 3 consecutive errors, every time... I tried switching API keys, locations via Proxy, different extensions, but the outcome is the same. The model config in VSCode itself is correct, 1048576 tokens input context, 131072 tokens output context, with tooling tag applied to it.

What might cause such problem? I can't really use the model for long-context tasks since I need to open a new chat every time.

My API url query for GLM-5.2: https://integrate.api.nvidia.com/v1/z-ai/glm-5.2

reddit.com
u/Salat_Leaf — 26 days ago

Help on ML-KEM and AES post-quantum security levels

According to NIST, ML-KEM -512, -768 and -1024 stand for AES-128, -192 and -256 post-quantum security levels respectively. However The Grover's algorithm speedup will half the security of symmetric ciphers

Why would we consider using ML-KEM-1024 if AES-256 will get weakened to 128 bits? Is there a practical reason?

Thanks in advance!

reddit.com
u/Salat_Leaf — 26 days ago
▲ 20 r/i2p

Any I2Pd decentralized mailing client?

I got I2Pd, all set and correctly configured, POP3 7660 pop.postman.i2p port 110, SMTP 7659 smtp.postman.i2p port 25, SAMv3 7656/7655 TCP/UDP, HTTP 4444 and SOCKS 4447 outproxy.

However I don't know any clients for I2Pd that would let me create addresses like "name@domain.i2p" while being decentralized. I'm on Win11, so I tried pboted, but as it seems it's not the best solution.

What are the good services for I2Pd mailing? Could you also provide references how to set them up on Win11, or where to start. Appreciate your help!

reddit.com
u/Salat_Leaf — 1 month ago

What's the best way to rewrite CUDA code into Vulkan CU?

The title is a bit vague, so lemme elaborate. I got to deal with post-quantum cryptography, specifically ML-KEM/Kyber. There's an implementation written in CUDA in liboqs suite (cuPQC). I'm a bum when it comes to Vulkan, but I know it's possible to use compute units to make GPU acceleration cross-platform. My strong requirement is a fixed code base, so I could run it on Nvidia, AMD, Intel, ARM SoC, Apple Silicon and even RISC-V based GPUs.

How can I achieve that without redoing all the work by myself? If so, what are the tools you might recommend me to assist in code rewriting. If not, may you refer to some materials regarding Vulkan compute units and some low level control for purely background calculations (no display output needed, however I might consider implementing seperate UI in Vulkan, not related to the aforementioned calculations)

reddit.com
u/Salat_Leaf — 1 month ago

Star level 3 Pekka, MK, Valkyrie

Skins in Chinese version that would perfectly suit the game as a star level 3 version of troops. Like the assets and written code is already there, strange they don't add it in the global version :/

u/Salat_Leaf — 1 month ago

What's the best compression algorithms for each executables?

I'm making an app which I compile into one single executable for each CPU model of the following architectures (x86, ARM, Loongson and PowerPC). Since we know the range of each instruction set of each CPU, may you recommend some compression algorithms that would fit best for each platform.

There's no any static image or sound metadata within the executable, no GUI framework is used, everything is draw rawly with VulkanAPI. The only static data is some static arrays and precalculated vertex positioning arrays for graphics primitives (-1 to 1 coordinates)

reddit.com
u/Salat_Leaf — 2 months ago

Hot/Cold/Quantum superposition take

This community is biased as fuck, my pancreas produces less juice than this community. No matter what devs do, players are always emanating pointless hatred. I'm surprised by the amount of people without critical thinking over there. Let's address a couple of things to make it clear:

  1. The "Yes yes" option in the latest event - are we deadass? It's a joke, and people are triggered by anything nowadays

  2. "Let the game die!" - there's a thing as secondary projection upon yourself from critiquing somebody else. Even of the devs are there just for a paycheck, do you have any idea that YOU may be the fault that you judge them harshly by any bad (and even somewhat mediocre/good) decision they do? Have you had an idea the team is silent because they're trying to escape this vicious community? And even when someone interacts with anyone, you mfkes spill everything onto a person that got almost nothing to do with 99% of your problems. What would YOU do in this situation? Would you like it if you were threated that harshly? Have you once asked yourself why devs only listened to creators?

  3. "Balancing is awful, heroes, evos, they all ruin the game!" - Let me ask all of you: if you think that this monetary policy is bad, then what would YOU do to earn money and keep the game alive simultaneously? Adding shit tons of skins? You want it to become another Brawl Stars, in which you can't recognize characters unless you're a sweat? Or maybe you know how to balance the game better to satisfy everyone? You know top 1% is not the whole game right? People haven't learned nothing from Elixir golem rollout experience with rapid balance changes I see..

  4. "The game is boring!" - The why the fuck are you complaining? Are the devs your personal circus? Why are you posting that you deleted the game? You want to feel validated from nonames online and feel proud of yourself? Congratufuckinglations! You just contributed to the reason why devs don't listen to us! Most of your reasoning is "This game sucks because". You feel bored - delete and don't complain, maybe return in while, as long as you have ACTUAL FUN, this is rhe the point of A GAME.

Now, since I feel much easier after addressing all of this bullshit and most ADHD kids who have already left, unable to finish reading the text, feel free to express your non-biased opinion with supportive argumenrs on all of this Idiocracy. I respect everybody who doesn't seek validation of their blatancy. Main clash royale subreddit automatically deletes my post, however I'm not going to filter my speech. This genuinely infuriates to play my favorite mobile game surrounded by the majority of jerks

reddit.com
u/Salat_Leaf — 2 months ago

Questions about x86 RDRAND/ARM RNDR/PowerPC DARN DRBGs

I've read some of the intel documents and only know that RDRAND in x86 is basically AES in CTR mode with 128-bit prediction resistance, and refreshing itself on every AES block (basically AES-128). But where does it take its entropy from? Is it just a one time proceedure by obtaining a True RNG from RDSEED and then deriving keys from it? What about other architectures like ARM and PowerPC? How are their implementations of CSPRNG different from x86 in all of aforementioned things?

reddit.com
u/Salat_Leaf — 2 months ago

Elaboration on ChaCha

Are there any sources you might recommend to read more about ChaCha? What's the exact math that lies within it? Why is the key size and nonce exactly as they are (e.g. nonce as 96-bit/192-bit XChaCha, instead of, say, 128-bit and 256-bit), and what is the the quarter round and why is ChaCha split into two different types of rounds?

If you know some article on that you may refer to or just explain the math directly, I would like to hear more

reddit.com
u/Salat_Leaf — 2 months ago

I own consumer Intel 13th gen CPU with VAES support (+AVX512 implicitly)

Basically, I tried to run AES intrinsics on my CPU and notcied __VAES__ macro was defined, indicating it's support. It's not shown in CPU-Z, but I tried to inspect the disassembly and I found out it has been using ZMM and YMM registers on vaesenc instruction and my laptop didn't crash when I compiled my program with AVX512 and VAES flags. The output is successfully calculated using VAES 256-bit intrinsics.

Idk how rare it is tho, but I guess it's quite rare

u/Salat_Leaf — 2 months ago

How does my CPU run unsupported instructions?

I've got Intel i7-13620H. My supported instruction set list in CPU-Z:

MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, AES, AVX, AVX2, AVX-VNNI, FMA3, SHA

However, when I conditionally compile my program with __VAES__, the macro gets automatically defined at compile time, I even tested it specifically with __attribute__((target("aes,vaes,avx512f"))), it runs without some purple unsupported instruction error that would otherwise appear (at least it does show up on Windows). I checked the assembly, the compiler does not optimize the intrinsics. VAES is only available on AVX512-supported hardware. However, when I run 512-bit version of vaesenc itself, it fails to produce the output when I try to print it in terminal, while 256-bit version successfully computes the result.

How is this possible?

reddit.com
u/Salat_Leaf — 2 months ago

What's the fastest general lossless compression algorithm (C/D, pure D)

From what I've seen so far, LZturbo is the fastest general lossless compression/decompression algorithm, while ZXC is fastest for pure decompression. However LZturbo is also closed source. I wonder if there are any faster alternatives to these algorithms in each class

reddit.com
u/Salat_Leaf — 2 months ago