What do you think of my idea? HARDFUCK - Brainfuck but for Hardware!
who wouldn't want that!
I'm currently designing a bare-metal Brainfuck core for FPGAs and wanted to get some feedback on the architecture before I start writing all the Verilog.
Tape Architecture (Memory-Mapped I/O) The tape works like standard Brainfuck, but with negative addresses (or pointer overflow) mapped to hardware registers instead of normal RAM:
- -1: Raw GPIO Data Register (0b00000000 = all off). Using
.and,to set/read pins to prevent setting stuff on accident. - -2: GPIO Direction Register (0 = input, 1 = output).
- -3: Analog IN (ADC).
- -4: Access to instruction memory itself (read/write).
- -5: Configuration (pin mapping for serial/PWM etc.).
- -6 to -8 (Copy addresses): Set source address at -6, dest at -7, and writing to -8 via
.triggers a fast 1-cycle DMA copy from A to B.
Instruction Memory (4-Bit Encoding)
- Bit 0: Flag bit (0 = standard BF instruction, 1 = empty/NOP, jump label, or extended ops like bitwise shifts).
- Bit 1-3: The 3-bit instruction (0 =
>, 1 =<, 2 =+, 3 =-, 4 =., 5 =,, 6 =[, 7 =]).
Bootloader Simple approach: Pulling a pin low on reset (or a specific serial sequence) overwrites instruction memory. Since instruction memory is accessible at -4, you could even write a native BF bootloader that reads a new program from serial and writes it straight to memory.
Loops Either a counter tracking nesting depth to scan forward/backward, or just a tiny hardware stack for jump addresses.
What do you guys think? Any suggestions on what else to add to the negative address space?
btw: I only found out about https://www.youtube.com/watch?v=QloNq8AoHvU after I already made this concept, it a similar idea and would be a cool endproduct but the philosophy and design are diffrent (even thoug i could probably design it for that hardware)
