u/Primary_Olive_5444

Intel still has the biggest say in Mobileye.

CEO Professor Amnon Shashua stepping down (maybe he got forced out, but it's about time he goes).

The board is tasked to find a replacement.

Chairman Safroadu (ex-Intel, he left in April 2025), bought shares on 6th Aug
And the infamous Frank Yeary also acquire stakes on 30th July.

https://www.nasdaq.com/market-activity/stocks/mbly/sec-filings

https://ir.mobileye.com/corporate-governance/board-of-directors

https://preview.redd.it/7mnw686a8gjh1.png?width=973&format=png&auto=webp&s=2425a77ead0c4ee8a02d4fb9ccee39859a1423cd

That brings me to the game for Mobileye. Obviously the company need a new CEO, new product offering or maybe investors with cash to move the stock price up.

Borrowing on Arm's presentation slide:

https://preview.redd.it/w3q8lu1g9gjh1.png?width=1565&format=png&auto=webp&s=1516a55e659a485a11ead420b734a72d0ce0e595

Nvidia captures the cloud and data-center in the early AI training game (hence it's $5T now) and clinging onto that place. They can struggle hold TSMC wafer allocation.
Other chip design (fabless player) will have tough time on the supply, since it's akin to a blockade on the Straits of Hormuz.

Apple captures the Edge AI (row) Iphones, Mac Mini, Macbook/Ipad with the highest profit margins by far (before Nvidia overtook them as the most valuable company).

Physical AI -> which is still up for grab. Any companies that can expand their presence there, will most likely benefit from higher/bigger market valuation (which is good if you have those shares/call options). And Intel have like a 70% stake in Mobileye.

Why? Because it's a market expansionary move, and expansion always see higher valuation if it comes with positive/high margins growth.

Intel Foundry makes the semiconductor that can work across the entire spectrum.
A good process node like Intel 18-AP or Intel 14A helps to win pockets of the physical AI segment.

So can the new incoming CEO of Mobileye leverage on Intel to bring business in the Physical AI space?

Intel do have some cash from the recent Equity Offering ($20 billion).

The new guy have to figure out the Physical AI play (which Mobileye already bet on.
Robotaxi and Robotics) and workout how best to leverage Intel's current momentum and resources.

Software layer, Intel Foundry, Altera's FPGA etc.

In January, they announced acquisition of Mentee Robotics, follow by offering Robotaxi business in US starting in 2027.

https://preview.redd.it/he216ascdgjh1.png?width=843&format=png&auto=webp&s=02fd92638f828f5d33660da6aa77837ca6884fc8

From a chart perspective, small tiny candles within a narrow band of late (consolidation at play??) and waiting for news/announcement to pop (i hope it's upwards, because Intel stands to benefit).

Maybe that ties in with the recent buys from the directors.

https://preview.redd.it/qh753of0fgjh1.png?width=1374&format=png&auto=webp&s=bb4e89715b90ef448bd2939e355a687b1b592136

Ticker: SE UN (ADR) later but we got to talk about Tencent first to get the picture.

Tencent (0700.HK) just reported their earnings (2Q2026) this week. As expected revenue growth was just okay up 11% (YoY) and up 4.2% sequentially (QoQ)

As a tech giant (comparable to the US hyper scaler), the common topics that get focused on during earnings call these days are CAPEX number and Free Cashflow.

Numbers:
2Q2026 Total Capex was 52.8billion (RMB)
up 176% YoY and +65% QoQ.

Free Cashflow goes to negative 13.8billion (RMB) in 2Q2026

So either they continue with that spending rate or shift elsewhere in this AI race.

https://static.www.tencent.com/website-2026-upload/2Q26-earnings-PPT_20260812_1800-88b183.pdf

To stay in the AI race:
You can borrow via bond issuance or equity placement like what (Intel just did)or divesting assets.

So the path that Tencent will take are (most likely):

1. leverage up with some bond issuance in HKD or RMB.

2. Divestment of their assets (so that brings me to their investment in listed/unlisted companies)

Divestment in 2026 (YTD) news:
https://www.businesstimes.com.sg/companies-markets/tencent-talks-offload-marvelous-and-other-global-game-bets

https://www.reuters.com/world/asia-pacific/tencent-unit-seeks-up-155-billion-kuaishou-share-sale-term-sheet-shows-2026-07-06/

In July, they pared down their stakes in a HK company at a very depress price level.
But they need the cash, so it must go on.

Triangulating onto SE:
The last time Tencent sold stakes in SE (Sea Limited ADR) shares was back in early 2022. Before the Fed went on hiking cycle and tanked the share price.

https://www.straitstimes.com/business/companies-markets/tencent-plans-to-sell-a-stake-in-singapores-sea-for-up-to-4-billion

It has been awhile since that last offload (4 years+ back) and Tencent now needs to fund it's AI Capex more than ever. Which is the obvious part.

Based on reported numbers, Tencent still holds a 16% stake in Sea Limited ADR. There's room to bring that number down and re-allocate capital for their AI and Agentic AI.

Sea Limited also just reported earnings this week, so the play here is simple. If Tencent wants to offload like a 5% stake figure then it will be at a discount to the last traded price just to get the buyers in
Which creates selling pressure in anticipation.

Do have questions on this topic.
Some over-simplification here, but i'm still trying to grasp eFPGA.

Maybe first start off with: Discrete FPGA vs eFPGA

Where eFPGA is either on the same monolithic tile as the main compute SOC (generally speaking) or potentially in the form of chiplet/tile within the same substrate package.

eFPGA, if monolithic setup will need to have the same design rule compatibility. Which of course eats into transistor budget (for advanced logic,SRAM array), actual die area (mm^2) and fabrication.

If chiplet approach, that relies more on advanced packaging for the connectivity bandwidth but the energy consumption and latency will beat out a discrete FPGA that needs communication via PCIe connectivity.

Basically, you avoid paying the round trip penalty of going with discrete FPGA.

Compute -> eFPGA vs GPU

Prefill is about prompt consumption and getting the KV cache.

GPU (referring to iGPU) it's SIMT ("Single Instruction Multiple Thread"), but launching threads has it's overhead. Which realistically i don't need to pay if what i'm after are KV cache values.

And GPU silicon isn't configurable (hard IP, whatever nvidia PTX or intel sycl instruction that it ships with, it can only execute those)

eFPGA - Logic elements can be reconfigured on the fly (if the bitstream values is send fast enough to the FPGA controller for setup and routing of the logic elements). Any change in local/on-device models can be tweaked when updating the software.

If KV cache workload is very much deterministic that set of calculation can be further accelerated on a FPGA. And reconfigure when new models comes out if there are enough logic elements on the chiplet eFPGA to support it.

https://arxiv.org/pdf/2603.20397

Monolithic (same process node)	Compute tile -> 18A	eFPGA -> 18A
Chiplet/tile	Compute tile -> 18A	eFPGA -> Intel 3 or Intel 7 or TSMC

From chipsandcheese (meteor lake writeup)

Advanced packaging to glue up the tiles from Intel Meteor Lake.

eFPGA vs Discrete FPGA (xilin or altera)

eFPGA die size gets smaller since it leverage on the same IP in the SOC. Memory Controller, Memory Pool etc.

I'm quite interested to understand the micro-architecture of Cerebras Wafer Scale Engine and fabrication of the circuitry.

From their 2026 Q2 earnings:

• Supply Chain Capacity Expansion: Secured TSMC wafer supply needed for continued growth. Well positioned with other component vendors to meet the rapid growth forecasted in 2027 and beyond.
• Supply Chain Advantages: Through our wafer-scale architecture, we avoid many of the components that are currently in short supply. We do not use HBM memory, CoWoS packaging or 3nm fabrication technology, all of which are currently supply limited.

https://preview.redd.it/c7x1awvri2jh1.png?width=1460&format=png&auto=webp&s=b7c4371d45e4f25d614345766d19c36ad3dd0bf0

The key appeals of this product in semi-conductor manufacturing are:
SRAM Memory and redundancy
Massive amount of SRAM on a single wafer that side-step the need for HBM and advance packaging.

Since you are looking at the whole wafer, they can live with much higher defect density on the output. Just bin/fuse off the portion of the chip that failed during production.

Connectivity:
The compute foot-print is big, backed by the memory before it has to spill out to another connected wafer.

But in my view, it's just an accelerator for targeted compute workload (not general purpose workload, like a CPU).

In a CPU, there are the branch predictor, out-of-order scheduler and instruction decoder circuitry that you need to litho and etch onto wafer.

And CPU are the workhorse for agentic AI workflow.

Question:
Is the Cerebras Wafer Scale Engine, designed to handle general purpose workflow directly on the same wafer right now?

i.e. on that wafer hardware (without a x86 or aarch64 host CPU) it can run linux OS?

Have Cerebras ever mentioned if they have a preferred ISA or a plan to adopt which ISA for general purpose compute?

x86_64, aarch64 or risc-v

Maybe the market is reaching the fatigue stage of the AI run, mix in hyperscaler burn on free cashflow to fund buildup via "Circular Funding" both creates anxiety.

On the point of circular funding, if you look at it from the lens of "global trade" (import and export) isn't that the same methodology. One needs to spend so that the other consumes, unless it's back to the colonial age of extracting resources thru force.

So companies like Apple, JP Morgan and Big Pharma will have to join in the funding game sooner or later.

But LLMs doesn't really allow you to win in the new cold war era, but advancement in new Material Science does. Because you ultimately need hardware (i.e. something tangible) to deal with your adversary and to come out on top.

US needs to find a off-ramp from AI somehow to spin a story to continue the compute game.

CPU (cloud virtualization) -> GPU/ TPU / fast networking (parallel computing, AI LLMs) -> FPGA -> QPU (quantum process unit)

To the main course:
IBM was in the news recently, a $10 billion CAPEX spent over 5 years to press on with Quantum Computing.

https://preview.redd.it/um6tkuuwg2gh1.png?width=1192&format=png&auto=webp&s=400c8f9f69c5f5afd76b87eae4337c7e868f7b1d

You spent money where you can see/predict a positive ROI. That IBM capex triggered my chain of thoughts and to connect the dots on what they are up to exactly.

https://newsroom.ibm.com/2026-07-23-ibm-to-acquire-hrl-laboratories-to-power-the-future-of-quantum

https://preview.redd.it/kcc1zzeui2gh1.png?width=790&format=png&auto=webp&s=8a01e290ebfca1a20a64fc17bf8d9f378f41bb07

IBM has traditionally been focus on Super-Conducting Qubits for QC, whilst Intel (because of the CMOS and manufacturing expertise) has been on the side of Silicon Spin Qubits.

Silicon Spin is more geared towards high volume manufacturing because of the supply chain in CMOS. But super-conducting has a material constraint that limit high volume production.

So it seems like IBM is either trying to do path-finding in silicon spin to spread the bets on QC or IBM researcher has uncovered something new in silicon spin and hence the investment to acquire HRL labs. I believe the latter is more realistic.

That bring us to Intel (foundry + intel labs), IBM and ASML EUV machine for Spin Qubits production.

Intel foundry has high-na EUV machine sitting in their fabs and have hands on experience using it in actual Intel 18A production. Those expertise are important because ASML machine are not easy to operate with.

Intel Labs has a working prototype, Tunnel Falls (12 qubits) research chip.
https://newsroom.intel.com/new-technologies/quantum-computing-chip-to-advance-research

But for actual quantum computing to have a profitable commercial use case, it needs millions of qubits, error correction + fault tolerance and high coherence. Those are not easy things to solve in silo.

Revisiting history:

For x86_64, that involved cross licensing between AMD and Intel to move things into the 64-bit computing era. Intel for it's part was good with manufacturing and scale up production.

IBM does have lots of patents and Intel can do up the manufacturing at scale. So something like a cross-licensing agreements (between IBM and Intel) can speed up the advancement of QC much quickly.

For the stock market to continue pumping, it needs a new "story spin" in computing that doesn't revolves around LLMs content.

https://preview.redd.it/d9ucbex8k2gh1.png?width=911&format=png&auto=webp&s=8211dbb3470edf3ada2e82f2e80db6ebd8b82e3b

https://www.imec-int.com/en/press/world-first-imec-presents-quantum-dot-qubit-device-using-high-na-euv-lithography

As it stands, Intel (DCAI) rack scale solution roadmap seems to be integrated with SambaNova RDU (SN50 latest gen) for the inference battleground.

https://preview.redd.it/zwd1bhp9psfh1.png?width=901&format=png&auto=webp&s=fb229b9344dcc86dfc3c060894f0c6c82d56dc9f

The setup would be Intel Xeon 6 (Granite Rapids) + SambaNova (RDU) + Nvidia (GPU).

Jensen is too close to TSMC, so we can count him out to tap on Intel Foundry.

Rodrigo Liang (CEO of SambaNova) is close to Lip Bu and they need to ramp production because they just signed up banks like JP Morgan who is looking to deploy their RDU stuff.

https://sambanova.ai/products/sambarack

From the 2024 hotchips production deck, the SN40L was made on TSMC 5nm with advanced packaging (CoWos) and slapping on 64GB HBM.

https://preview.redd.it/nr070acplsfh1.png?width=1201&format=png&auto=webp&s=019e521d703b62784cbb51ab6d95826e8a09aeb4

Maybe in a future product release, the SN?0 version can look to internalize sourcing from Intel Foundry directly.

Process Node -> Intel 18A-P or Intel 14A for the RDU.
Advanced Packaging -> EMIB
HBM -> switch over to Intel+Saimemory Z-Angle Memory (ZAM)

Paired with Intel Xeon 7 (Diamond Rapids) for agentic inference.

https://preview.redd.it/2swqy3lonsfh1.png?width=852&format=png&auto=webp&s=0955e6502be45fcf394d191bb92140b8fe98f269

Old news from Sept 2024, but the biggest rewards are often uncovered after connecting the dots with old news.

Back then, Intel announced a custom AI "Fabric" Chip made on Intel 18A with AWS.

As it currently stands (based on available info online)
Intel makes custom Intel Xeon 6 Granite Rapids with AWS (old news from like 2H2025) and AWS own ARM Graviton CPU uses Intel's EMIB for advanced-packaging.

But as of late there hasn't been much news between this pair over last 4 months or so.

And not much details have surface about the AI Fabric Chip made on 18A, but looking at silicon tape-out cycles (which is usually 1.5-2 years period), we should be expecting some news getting release soon.

https://preview.redd.it/i2oo02n1kych1.png?width=1749&format=png&auto=webp&s=0ec9fdb9ee4dd13a44b873fee93466602203383d

https://community.cadence.com/cadence_blogs_8/b/ip/posts/cadence-achieves-successful-silicon-validation-of-first-ip-testchips-on-intel18a

Until i came across this piece of blog uploaded by Cadence (EDA software vendor) back in May.

The odds are (my speculation here) that within the next 1-2 months we may see a disclosure about the AI Fabric chip (which from researching on AWS+Annapurna labs) is a custom AWS switch chip (similar to what Nvidia & Broadcom currently sells like hotcakes).

High speed networking switch chip over at the foundry side is denominated by just 1 player, TSMC only. Samsung foundry is no where there for SerDes products.

Nvidia (Mellanox) and Broadcom (Tomahawk/Jericho) sells the final silicon to hyperscaler and HPC customers.

Good news (if my speculation turns out correct)
Intel 18A process node is no longer confined to just CPU type products (Panther Lake and Xeon 6+ clearwater forest), but will be expanding out towards switch chip product segment.

And data-center switch chips products are of course higher margins product which is what Intel needs right now.

https://preview.redd.it/zzajj35ikych1.png?width=1725&format=png&auto=webp&s=7a468b8f6fab8c71b4a311a257c87d072a15c456

https://preview.redd.it/k3uoc3k0jwch1.png?width=1840&format=png&auto=webp&s=f6f1d0a05aed9e6818f6f69e1b3f98112c5adfc7

BWXT commercial operations will likely be an increasingly material source of growth as utilities invest in nuclear reactor life-extension projects.

Bond issuer rating upgraded from BB- to BB+.

Intel still owns a 49% stake in Altera after divesting the other half to Silver Lake.

https://www.reuters.com/business/altera-returns-growth-ai-robotics-fuel-demand-ceo-says-2026-07-10/

Altera, a maker of programmable chips spun out of Intel (INTC.O), opens new tab, is growing roughly 20% a year and more than doubling operating income as it ​prepares for an eventual public listing, Chief Executive Raghib Hussain told Reuters in ‌an interview.

Connecting the dots, back in Sept 2025 Altera held a Investor day keynote.
In that keynote, they did a official launch of the Altera Agilex series of FPGA for edge and data-center usage, made on FinFET transistors with advanced packaging from Intel Foundry.

Intel 10nm & Intel 7
Chiplets

https://preview.redd.it/cblwx07ejtch1.png?width=1868&format=png&auto=webp&s=bed037f2fb45e31997dd827e11117c6f24c276d0

https://www.youtube.com/watch?v=64I-z5ASIM4&t=7225s

Intel foundry are using DUV lithography only with SAQP for those 2 nodes + advanced packaging (EMIB 2.5D) with other chiplets or HBM on the same sustrate.

Since Intel 10nm & Intel 7 are matured nodes by now, the defect rates and yield (depending on the die size), would be a cash-generator and helps to improve EMIB manufacturing steps.

https://preview.redd.it/9tnsc5ijktch1.png?width=1089&format=png&auto=webp&s=0fe95a320af581d22b0d20119bac4c7182d4895f

A classic example of earning "double" (Foundry + Altera) margins when the foundry process node+advanced packaging is been used on a product that is seeing demand from the street.

JP Morgan will deploy SambaNova.
Hopefully that increase the sales of Intel Xeon 6 (Granite Rapids) as well.

Xeon 6 (made on Intel 3) should be seeing decent yield + low defects. So that's a cash generator.

https://preview.redd.it/a3ftc0zllybh1.png?width=1362&format=png&auto=webp&s=43fce85a0545c44aa7ee0565f187985a4ed87579

https://preview.redd.it/xrby8tl1mybh1.png?width=1650&format=png&auto=webp&s=1327c7b9bc04c1565b2a019cda126b215e06b6fb

https://preview.redd.it/aoxye1p6iwbh1.png?width=2342&format=png&auto=webp&s=c14f0c4c6cd09143d619477e7408c3e177425f80

Couple of years back Intel released the Max SKU series of Intel 4th Gen with HBM2E (64GB capacity).

https://www.intel.com/content/www/us/en/products/details/processors/xeon/max-series.html

That product launch wasn't particularly well received, due to teething issues (bios and numa configuration) and market needs back then (less AI focus).

Intel also was struggling with process node development stuff due to missing out on EUV adoption for those nodes and had to lean heavily on ASML DUV with self-aligned quad patterning. So core count was bad (lower) and the mesh interconnect for multiple cores was slower.

https://preview.redd.it/9snl8t50kwbh1.png?width=2232&format=png&auto=webp&s=4a3ce3316c9d954d1a97d5c710a282253f758b68

But fast forward things to current day, memory (GDDR, DDR, LPDDR) is in short supply and customers have to pay up to procure it and pass on cost to consumers (hyper-scaler/enterprise).

So the big question is can Intel (DCG) and Intel Foundry worked on a product that source in-house memory production and combine it with the latest Xeon 6 (granite rapids) or Diamond Rapids.

In-house production of custom memory that is HBM like and provide LINUX OS compatibility would ease the supply chain. It doesn't need to be a high volume production but just sufficient to meet the demands of customers. Since Intel already make the CPUs why not have a "custom" version of HBM/XBM to go along with it.

Customers would be willing to pay if the latency and troubleshooting is seamless like current HBM pairing.

And you earn double margins.. margins from CPU and custom XBM.

https://preview.redd.it/5thcr9w8jwbh1.png?width=1536&format=png&auto=webp&s=3dbfa049ebf7434963b4f25478bf7bc83c7ff35b

https://preview.redd.it/sqint6o4rd9h1.png?width=2141&format=png&auto=webp&s=082fa675263283e40d33bd53b6b4cb465e7f91bf

TLDR -> is the accelerator just a glorified memory controller, somewhat?

Qualcomm presented in their 2026 investor day a new form of technology (which looks very odd to me because it's staking Memory on top of Logic), which they brand/market as "HBC" aka High Bandwidth Compute.

Logic will do some form of computations and have some SRAM for register files etc. But heat will get trapped because thermal needs to get radiated out somehow.

HBM is sticking of DDR memory (12-16 layers high) and using a base silicon interposer for the signal bus routing (1024 bits bus) over into the SOC.

In Qualcomm's slide they replace it with LP-DDR (which is still DDR but with a narrower bus-width and maybe the memory controller uses lower power).

And since it shows TSV, which means the holes drilled into the memory stacks are most likely stagger left-right-left (Top layer 0 -> 16 bits left, layer 1 ->16 bits right, layer 2 -> left with some offsets).

That increase memory capacity (e.g. total 256GB LPDDR stack) but memory bandwidth will still be low.

That brings me to the part where it seems like the accelerator will do some math compute and just send across to the SOC the necessary results or reducing data movement size (in GB bytes). Essentially doing some "prep" work and then routing the "optimized data" over to the SOC.

Because it's optimized it can reduce the "total overall" data footprint that needs to be routed. Moving data consumes more energy, so the lower amount of bytes i move the lower the energy measuring using pico-joules per bit

TCO -> Lower
(technically correct, since you don't need interposer for that big of signal routing to the SOC compared to HBM usage)

Energy -> Lower
(technically correct, because using LPDDR and a narrower memory bus to the SOC lowers pico-joules per bit)

Complexity

For the accelerator to work, i can see a complexity in the software aspect (maybe LLM or coding agent can help reduce some of that mess).

1. Need to figure what kind of computation the accelerator is design for?
2. Talking to the SOC on what the accelerator have to send over and memory address (physical System Level Cache ("SLC"). The bulk of the workload is still handle on the SOC directly since it gets better thermal dissipation.

https://www.bloomberg.com/news/articles/2026-06-17/bwx-agrees-to-license-nuclear-reactor-design-after-activist-push

Takeaways by Bloomberg AI

• BWX Technologies Inc. has struck a deal to license its design for a small modular reactor after activist investor Ananym Capital Management pushed the company to consider commercializing it.
• Applied Atomics has entered a licensing agreement for BWX's mPower design, gaining exclusive rights to commercial use of the design in land-based facilities in the US, Canada and elsewhere.
• Core Power Inc. has launched a feasibility study to integrate the mPower design into floating nuclear power plants, while BWX will retain ownership of the design and hold exclusive manufacturing rights for all components.

Additional caveats:

Also Wednesday, ship-based nuclear energy systems company Core Power Inc. said in a separate statement that it has launched a feasibility study to see if it can integrate the mPower design into floating nuclear power plants that would be built and deployed from shipyards.

Lynchburg, Virginia-based BWX, which is also known by its stock symbol BWXT, confirmed the agreements with Applied Atomics and Core Power.

Ananym has been urging BWX to redevelop its mPower design, which was shelved in 2017. Making its push public at the Sohn Investment Conference in New York in May, Ananym Chief Investment Officer Alex Silver said BWX has the potential to more than double its market value by 2028 through licensing or developing the mPower design

Commercial revenue has indeed double (without even licensing out the design) based on past quarter financial.

https://preview.redd.it/uqod1gyn918h1.png?width=1914&format=png&auto=webp&s=e9129d7030c77e032da4f5f23ef2567110c36197

With the imminent / most hyped up IPO in a long while likely coming in June, SpaceX.

It go me thinking about space/satellite and the conquest for it by those who can build rockets.

To conquer space, you need power (solar or nuclear with HALEU) and semi-conductor (compute, communication and robotics for repair works when it needs servicing).

Back when Pat G was still around, he signed UMC (Taiwan Foundry, legacy node player) with Intel IFS. They worked on / taped out a 12nm chip which is more for analog oriented operations.

With 12nm, it's a FinFET node and with lithography steps that requires just DUV.
And Intel is good with DUV, since they got experience with it on the 10nm doing SAQP ("self aligned quad patterning") for advanced logic products.

I reckon the yield is high and good enough for the 12nm products to make $$.

United Microelectronics Corporation (UMC) brings together Intel Foundry’s at-scale US manufacturing capacity and UMC’s extensive foundry experience on mature nodes to enable an expanded process portfolio for select applications.² The node is ideal for radio frequency (RF) transceivers, satellite systems and cost-sensitive defense electronics.

Then the monetize question would be are there customers for it and what are the market alternatives right now from other foundry players (GlobalFoundries, Tower Semi, TSMC, Samsung Foundry) for advanced analog products to be used in space (compute and commuication)

Customers with deep pockets -> SpaceX and Blue Origin